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Searched refs:bitsLE (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h298 bool bitsLE(EVT VT) const { in bitsLE() function
H A DSelectionDAG.h862 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
878 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h414 bool bitsLE(MVT VT) const { in bitsLE() function
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp1928 assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatRes_LOAD()
1965 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1977 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1981 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1997 if (isSigned || SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
2288 assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatOp_STORE()
H A DLegalizeIntegerTypes.cpp917 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); in PromoteIntRes_INT_EXTEND()
3681 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ANY_EXTEND()
4066 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntRes_LOAD()
4814 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_SIGN_EXTEND()
4846 if (EVT.bitsLE(Lo.getValueType())) { in ExpandIntRes_SIGN_EXTEND_INREG()
5135 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ZERO_EXTEND()
5608 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntOp_STORE()
5769 assert(PromEltVT.bitsLE(NOutVTElem) && in PromoteIntRes_EXTRACT_SUBVECTOR()
H A DLegalizeVectorOps.cpp1230 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1289 if (SrcVT.bitsLE(VT)) { in ExpandZERO_EXTEND_VECTOR_INREG()
H A DSelectionDAG.cpp1145 EltVT.bitsLE(Op.getValueType()))) && in VerifySDNode()
1519 if (VT.bitsLE(Op.getValueType())) in getBoolExtOrTrunc()
1536 assert(VT.bitsLE(OpVT) && "Not extending!"); in getZeroExtendInReg()
1554 assert(VT.bitsLE(OpVT) && "Not extending!"); in getVPZeroExtendInReg()
6123 assert(N1.getValueType().bitsLE(VT) && in getNode()
6163 VT.getVectorElementType().bitsLE(N1.getValueType()))) && in getNode()
6220 VT.getVectorElementType().bitsLE(N1.getValueType()))) && in getNode()
7090 VT.bitsLE(N1.getValueType()) && in getNode()
7104 assert(EVT.bitsLE(VT.getScalarType()) && "Not extending!"); in getNode()
7119 assert(EVT.bitsLE(VT) && "Not extending!"); in getNode()
[all …]
H A DLegalizeDAG.cpp2656 (DestVT.bitsLE(MVT::f64) || in ExpandLegalINT_TO_FP()
5607 assert(NewEltVT.bitsLE(EltVT) && "not handled"); in PromoteNode()
H A DTargetLowering.cpp4799 isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && in SimplifySetCC()
5113 (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && in SimplifySetCC()
H A DDAGCombiner.cpp6577 if (ExtVT.bitsLE(Load->getMemoryVT())) in SearchForAndLoads()
15109 if (LN0->isSimple() && LN0->getMemoryVT().bitsLE(VT)) { in visitTRUNCATE()
24267 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT; in visitCONCAT_VECTORS()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td1207 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1213 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
H A DRISCVISelLowering.cpp3872 assert((ViaIntVT.bitsLE(XLenVT) || in lowerBuildVectorOfConstants()
3875 if (ViaIntVT.bitsLE(XLenVT) || isInt<32>(SplatValue)) { in lowerBuildVectorOfConstants()
4120 ContainerVT.bitsLE(getLMUL1VT(ContainerVT))) { in lowerBUILD_VECTOR()
4318 if (Scalar.getValueType().bitsLE(XLenVT)) { in lowerScalarSplat()
4366 if (ExtractedContainerVT.bitsLE(VT)) in lowerScalarInsert()
4381 if (!Scalar.getValueType().bitsLE(XLenVT)) in lowerScalarInsert()
9225 if (Scalar.getValueType().bitsLE(XLenVT)) { in LowerINTRINSIC_WO_CHAIN()
9813 auto InnerVT = VecVT.bitsLE(M1VT) ? VecVT : M1VT; in lowerReductionSeq()
10775 getLMUL1VT(ContainerVT).bitsLE(ContainerVT)) { in lowerFixedLengthVectorLoadToRVV()
10838 getLMUL1VT(ContainerVT).bitsLE(ContainerV in lowerFixedLengthVectorStoreToRVV()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1153 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
H A DAMDGPUISelLowering.cpp4311 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()
H A DSIISelLowering.cpp1917 VT.getScalarType().bitsLE(MVT::i16)) in getPreferredVectorAction()
6665 return Op.getValueType().bitsLE(VT) ? in getFPExtOrFPRound()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1533 return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020(); in decomposeMulByConstant()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td1069 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
H A DLoongArchISelLowering.cpp1624 dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLE(MVT::i32)) in lowerSINT_TO_FP()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17132 AVT.bitsLE(Ty); in PerformVECREDUCE_ADDCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp25339 assert(MaskVT.bitsLE(Mask.getSimpleValueType()) && "Unexpected mask size!"); in getMaskNode()