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Searched refs:bitsGE (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h282 bool bitsGE(EVT VT) const { in bitsGE() function
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h400 bool bitsGE(MVT VT) const { in bitsGE() function
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp393 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { in ExpandINSERT_VECTOR_ELT()
4827 if (NVT.bitsGE(SVT)) in ConvertNodeToLibcall()
4870 if (NVT.bitsGE(RVT)) in ConvertNodeToLibcall()
H A DLegalizeFloatTypes.cpp950 if (NVT.bitsGE(SVT)) in SoftenFloatRes_XINT_TO_FP()
1127 if (Promoted.bitsGE(RetVT)) in findFPToIntLibcall()
H A DLegalizeIntegerTypes.cpp803 if (SVT.bitsGE(NVT)) { in PromoteIntRes_EXTRACT_VECTOR_ELT()
2656 if (ResVT.bitsGE(EltVT)) in PromoteIntOp_VECREDUCE()
2685 if (VT.bitsGE(EltVT)) in PromoteIntOp_VP_REDUCE()
H A DSelectionDAGBuilder.cpp709 PartEVT.getVectorElementType().bitsGE( in getCopyToPartsVector()
8485 assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) && in visitVPCmp()
8513 assert(EVLParamVT.isScalarInteger() && EVLParamVT.bitsGE(MVT::i32) && in visitVectorPredicationIntrinsic()
H A DSelectionDAG.cpp7931 assert(NVT.bitsGE(VT)); in getMemcpyLoadsAndStores()
12006 assert(CVT.bitsGE(VecEltVT) && "Illegal splat_vector element extension"); in isConstOrConstSplat()
12022 assert(CVT.bitsGE(NSVT) && "Illegal build vector element extension"); in isConstOrConstSplat()
H A DDAGCombiner.cpp6573 ExtVT.bitsGE(Load->getMemoryVT())) in SearchForAndLoads()
6594 if (ExtVT.bitsGE(VT)) in SearchForAndLoads()
22159 MaxEltVT = MaxEltVT.bitsGE(EltVT) ? MaxEltVT : EltVT; in visitINSERT_VECTOR_ELT()
27445 if (!isNullConstant(N3) || !XType.bitsGE(AType)) in foldSelectCCToShiftAnd()
H A DLegalizeVectorTypes.cpp3592 assert(N->getValueType(0).bitsGE(EltVT) && "Illegal EXTRACT_VECTOR_ELT."); in SplitVecOp_EXTRACT_VECTOR_ELT()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1189 if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) { in LowerSTORE()
H A DAMDGPUISelLowering.cpp3921 if (SrcVT.bitsGE(ExtVT)) { in performAssertSZExtCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2367 if (LaneT.bitsGE(MVT::i32)) in unrollVectorShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6883 ContainerVT.bitsGE(getLMUL1VT(ContainerVT))) { in LowerOperation()
14228 cast<VTSDNode>(N->getOperand(1))->getVT().bitsGE(MVT::i16)) in performSIGN_EXTEND_INREGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp27908 if (VT.bitsGE(SrcVT)) { in LowerFixedLengthIntToFPToSVE()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp50310 if (!N->hasOneUse() || !N->getSimpleValueType(0).bitsGE(MVT::i32) || in combineOrCmpEqZeroToCtlzSrl()
50320 N->getOperand(1).getValueType().bitsGE(MVT::i32); in combineOrCmpEqZeroToCtlzSrl()