/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineCopyPropagation.cpp | 146 auto Dest = TRI.regunits(CopyOperands->Destination->getReg().asMCReg()); in invalidateRegister() 147 auto Src = TRI.regunits(CopyOperands->Source->getReg().asMCReg()); in invalidateRegister() 180 MCRegister Def = CopyOperands->Destination->getReg().asMCReg(); in clobberRegister() 181 MCRegister Src = CopyOperands->Source->getReg().asMCReg(); in clobberRegister() 233 MCRegister Src = CopyOperands->Source->getReg().asMCReg(); in trackCopy() 234 MCRegister Def = CopyOperands->Destination->getReg().asMCReg(); in trackCopy() 496 MCRegister PreviousSrc = CopyOperands->Source->getReg().asMCReg(); in isNopCopy() 497 MCRegister PreviousDef = CopyOperands->Destination->getReg().asMCReg(); in isNopCopy() 700 MachineInstr *Copy = Tracker.findAvailCopy(MI, MOUse.getReg().asMCReg(), in forwardUses() 791 MCRegister Def = RegDef.asMCReg(); in ForwardCopyPropagateBlock() [all …]
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H A D | BreakFalseDeps.cpp | 124 MCRegister OriginalReg = MO.getReg().asMCReg(); in pickBestRegisterForUndef() 177 MCRegister Reg = MI->getOperand(OpIdx).getReg().asMCReg(); in shouldBreakDependence()
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H A D | MachineCSE.cpp | 302 if (!isCallerPreservedOrConstPhysReg(Reg.asMCReg(), MO, *MI->getMF(), *TRI, in hasLivePhysRegDefUses() 322 if (PhysRefs.count(Reg.asMCReg())) in hasLivePhysRegDefUses() 327 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg.asMCReg(), I, MBB->end())) in hasLivePhysRegDefUses() 396 if (PhysRefs.count(MOReg.asMCReg())) in PhysRegDefsReach()
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H A D | MachineCycleAnalysis.cpp | 120 !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) && in isCycleInvariant()
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H A D | MachineTraceMetrics.cpp | 726 MCRegister Reg = MO.getReg().asMCReg(); in updatePhysDepsDownwards() 756 TRI->regunits(UseMI->getOperand(DefOp).getReg().asMCReg())) { in updatePhysDepsDownwards() 924 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) { in updatePhysDepsUpwards() 943 MCRegister Reg = MI.getOperand(Op).getReg().asMCReg(); in updatePhysDepsUpwards()
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H A D | EarlyIfConversion.cpp | 266 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) in InstrDependenciesAllowIfConv() 396 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) in findInsertionPoint() 400 Reads.push_back(Reg.asMCReg()); in findInsertionPoint()
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H A D | MachineLoopInfo.cpp | 275 !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) && in isLoopInvariant()
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H A D | CalcSpillWeights.cpp | 70 MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg(); in copyHint()
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H A D | LiveRangeEdit.cpp | 346 LIS.removePhysRegDefAt(Reg.asMCReg(), Idx); in eliminateDeadDef()
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H A D | MachineLICM.cpp | 1029 if (!TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *MI.getMF())) in isInvariantStore() 1059 if (!TRI->isCallerPreservedPhysReg(CopySrcReg.asMCReg(), *MF)) in isCopyFeedingInvariantStore()
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H A D | RegisterScavenging.cpp |
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H A D | RegisterPressure.cpp | 524 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg())) in pushReg() 559 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg())) in pushRegLanes()
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H A D | ReachingDefAnalysis.cpp | 131 for (MCRegUnit Unit : TRI->regunits(MO.getReg().asMCReg())) { in processDefs()
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H A D | RegAllocGreedy.cpp | 420 MCRegister PhysHint = Hint.asMCReg(); in tryAssign() 1264 OtherReg.isPhysical() ? OtherReg.asMCReg() : VRM->getPhys(OtherReg); in trySplitAroundHintReg() 2255 OtherReg.isPhysical() ? OtherReg.asMCReg() : VRM->getPhys(OtherReg); in collectHintInfo()
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H A D | MachinePipeliner.cpp | 1291 return Reg.isPhysical() && TRI->isFixedRegister(MF, Reg.asMCReg()); in isFixedRegister() 2048 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) in computeLiveOuts() 2061 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) in computeLiveOuts()
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H A D | MachineVerifier.cpp | 148 append_range(RV, TRI->subregs(Reg.asMCReg())); in addRegWithSubRegs() 2838 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) { in checkLiveness() 2976 MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg())) in visitMachineBundleAfter()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetRegisterInfo.h | 100 return MC->contains(Reg.asMCReg()); in contains() 109 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains() 453 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg()); in regsOverlap()
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H A D | Register.h | 110 MCRegister asMCReg() const { in asMCReg() function
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLowOverheadLoops.cpp | 640 MCRegister NumElements = TPNumElements.getReg().asMCReg(); in ValidateTailPredicate() 674 RDA.getUniqueReachingMIDef(ElemDef, Operand.getReg().asMCReg()) == in ValidateTailPredicate() 676 Operand.getReg().asMCReg())) { in ValidateTailPredicate() 760 &MBB->back(), VCTP->getOperand(1).getReg().asMCReg())) { in ValidateTailPredicate() 799 &Preheader->back(), VCTP->getOperand(1).getReg().asMCReg())) { in ValidateTailPredicate() 984 RDA.getGlobalUses(MI, MO.getReg().asMCReg(), Uses); in ValidateLiveOuts() 1118 !RDA.hasSameReachingDef(Prev, MI, MI->getOperand(1).getReg().asMCReg())) { in AddVCTP()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXFMAMutate.cpp | 317 for (MCRegUnit Unit : TRI->regunits(AddendSrcReg.asMCReg())) { in processBlock()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIOptimizeExecMaskingPreRA.cpp | 99 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg())) { in isDefBetween()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 1130 if (llvm::is_contained(ContiguousRange, Tuple.asMCReg())) { in expandMultiVecPseudo() 1132 } else if (llvm::is_contained(StridedRange, Tuple.asMCReg())) { in expandMultiVecPseudo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsExpandPseudo.cpp | 772 MCRegister Scratch2 = I->getOperand(4).getReg().asMCReg(); in expandAtomicBinOp()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
H A D | MIRParser.cpp | 840 Reg.asMCReg(), MaybeInfo->DILoc); in initializeFrameInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | BitTracker.cpp | 344 (RR.Sub == 0) ? RR.Reg.asMCReg() : TRI.getSubReg(RR.Reg, RR.Sub); in getRegBitWidth()
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