Searched refs:aintc_write_4 (Results 1 – 2 of 2) sorted by relevance
| /freebsd/sys/arm/allwinner/a10/ |
| H A D | a10_intc.c | 110 #define aintc_write_4(sc, reg, val) \ macro
120 aintc_write_4(sc, SW_INT_IRQ_PENDING_REG(0), in a10_intr_eoi()
136 aintc_write_4(sc, SW_INT_ENABLE_REG(block), value); in a10_intr_unmask()
140 aintc_write_4(sc, SW_INT_MASK_REG(block), value); in a10_intr_unmask()
155 aintc_write_4(sc, SW_INT_ENABLE_REG(block), value); in a10_intr_mask()
159 aintc_write_4(sc, SW_INT_MASK_REG(block), value); in a10_intr_mask()
343 aintc_write_4(sc, SW_INT_ENABLE_REG(i), 0); in a10_aintc_attach()
344 aintc_write_4(sc, SW_INT_MASK_REG(i), 0xffffffff); in a10_aintc_attach()
347 aintc_write_4(sc, SW_INT_PROTECTION_REG, 0x01); in a10_aintc_attach()
350 aintc_write_4(sc, SW_INT_NMI_CTRL_REG, 0x00); in a10_aintc_attach()
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| /freebsd/sys/arm/ti/ |
| H A D | aintc.c | 88 #define aintc_write_4(_sc, reg, val) \ macro
102 aintc_write_4(sc, INTC_CONTROL, 1); in ti_aintc_irq_eoi()
109 aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F))); in ti_aintc_irq_mask()
116 aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F))); in ti_aintc_irq_unmask()
270 aintc_write_4(sc, INTC_SYSCONFIG, 2); in ti_aintc_attach()
276 aintc_write_4(sc, INTC_THRESHOLD, 0xFF); in ti_aintc_attach()
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