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Searched refs:addOperand (Results 1 – 25 of 236) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp466 Inst.addOperand(MCOperand::createReg(RRegs[getRegNum()])); in addRegGPRCOperands()
471 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getRegNum()])); in addRegGPRCNoR0Operands()
476 Inst.addOperand(MCOperand::createReg(XRegs[getRegNum()])); in addRegG8RCOperands()
481 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getRegNum()])); in addRegG8RCNoX0Operands()
486 Inst.addOperand(MCOperand::createReg(XRegs[getG8pReg()])); in addRegG8pRCOperands()
505 Inst.addOperand(MCOperand::createReg(FRegs[getRegNum()])); in addRegF4RCOperands()
510 Inst.addOperand(MCOperand::createReg(FRegs[getRegNum()])); in addRegF8RCOperands()
515 Inst.addOperand(MCOperand::createReg(FpRegs[getFpReg()])); in addRegFpRCOperands()
520 Inst.addOperand(MCOperand::createReg(VFRegs[getRegNum()])); in addRegVFRCOperands()
525 Inst.addOperand(MCOperand::createReg(VRegs[getRegNum()])); in addRegVRRCOperands()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp563 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
569 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
584 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
594 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
596 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
598 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
635 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp303 ITInst.addOperand(MCOperand::createImm(ITState.Cond)); in flushPendingInstructions()
304 ITInst.addOperand(MCOperand::createImm(ITState.Mask)); in flushPendingInstructions()
2516 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
2518 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
2520 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
2535 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2537 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2542 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); in addVPTPredNOperands()
2544 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredNOperands()
2545 Inst.addOperand(MCOperand::createReg(0)); in addVPTPredNOperands()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp261 .addOperand(MI.getOperand(0)) in expandJBTF()
268 .addOperand(MI.getOperand(1)) in expandJBTF()
269 .addOperand(MI.getOperand(2)); in expandJBTF()
271 TmpInst = MCInstBuilder(CSKY::JMPI32).addOperand(MI.getOperand(2)); in expandJBTF()
286 .addOperand(MI.getOperand(0)) in expandNEG()
287 .addOperand(MI.getOperand(1)); in expandNEG()
292 .addOperand(MI.getOperand(0)) in expandNEG()
293 .addOperand(MI.getOperand(0)) in expandNEG()
308 .addOperand(MI.getOperand(0)) in expandRSUBI()
309 .addOperand(MI.getOperand(1)); in expandRSUBI()
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H A DCSKYAsmBackend.cpp294 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
295 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
299 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
303 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
307 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
312 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
313 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
314 Res.addOperand(Inst.getOperand(2)); in relaxInstruction()
318 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
319 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp216 CompoundInsn->addOperand(Rt); in getCompoundInsn()
217 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn()
218 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn()
228 CompoundInsn->addOperand(Rt); in getCompoundInsn()
229 CompoundInsn->addOperand(Rs); in getCompoundInsn()
230 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn()
242 CompoundInsn->addOperand(Rs); in getCompoundInsn()
243 CompoundInsn->addOperand(Rt); in getCompoundInsn()
244 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn()
255 CompoundInsn->addOperand(Rs); in getCompoundInsn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp251 T.addOperand(Inst.getOperand(i)); in ScaleVectorOffset()
259 T.addOperand(MCOperand::createExpr(NewHE)); in ScaleVectorOffset()
283 Inst.addOperand(Reg); in HexagonProcessInstruction()
284 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
285 Inst.addOperand(S16); in HexagonProcessInstruction()
292 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
299 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
306 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
313 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
320 Inst.addOperand(MCOperand::createExpr(C255)); in HexagonProcessInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp77 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR8RegisterClass()
88 Inst.addOperand(MCOperand::createReg(Register)); in DecodeLD8RegisterClass()
148 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOARr()
164 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIORdA()
172 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOBIT()
173 Inst.addOperand(MCOperand::createImm(b)); in decodeFIOBIT()
182 Inst.addOperand(MCOperand::createImm(Field << 1)); in decodeCallTarget()
199 Inst.addOperand(MCOperand::createReg(AVR::R31R30)); in decodeFLPMX()
243 Inst.addOperand(MCOperand::createImm(k)); in decodeFWRdK()
270 Inst.addOperand( in decodeMemri()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/Disassembler/
H A DXtensaDisassembler.cpp72 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeARRegisterClass()
83 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeMRRegisterClass()
94 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeMR01RegisterClass()
105 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeMR23RegisterClass()
116 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRRegisterClass()
138 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeURRegisterClass()
208 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeSRRegisterClass()
223 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeBRRegisterClass()
239 Inst.addOperand( in decodeCallOperand()
247 Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm))); in decodeJumpOperand()
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstBuilder.h38 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
44 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
50 Inst.addOperand(MCOperand::createSFPImm(Val)); in addSFPImm()
56 Inst.addOperand(MCOperand::createDFPImm(Val)); in addDFPImm()
62 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
68 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
73 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
74 Inst.addOperand(Op); in addOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp88 SICInst.addOperand(RD); in emitSIC()
96 BSICInst.addOperand(R1); in emitBSIC()
97 BSICInst.addOperand(R2); in emitBSIC()
99 BSICInst.addOperand(czero); in emitBSIC()
100 BSICInst.addOperand(czero); in emitBSIC()
108 LEAInst.addOperand(RD); in emitLEAzzi()
110 LEAInst.addOperand(CZero); in emitLEAzzi()
111 LEAInst.addOperand(CZero); in emitLEAzzi()
112 LEAInst.addOperand(Imm); in emitLEAzzi()
120 LEASLInst.addOperand(RD); in emitLEASLzzi()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp86 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
99 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRF16RegisterClass()
112 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRF32RegisterClass()
123 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRX1X5RegisterClass()
134 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass()
145 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
156 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
167 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
178 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
189 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR128RegisterClass()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/Disassembler/
H A DLoongArchDisassembler.cpp63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); in DecodeGPRRegisterClass()
80 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo)); in DecodeFPR32RegisterClass()
89 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo)); in DecodeFPR64RegisterClass()
98 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo)); in DecodeCFRRegisterClass()
107 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo)); in DecodeFCSRRegisterClass()
116 Inst.addOperand(MCOperand::createReg(LoongArch::VR0 + RegNo)); in DecodeLSX128RegisterClass()
125 Inst.addOperand(MCOperand::createReg(LoongArch::XR0 + RegNo)); in DecodeLASX256RegisterClass()
134 Inst.addOperand(MCOperand::createReg(LoongArch::SCR0 + RegNo)); in DecodeSCRRegisterClass()
143 Inst.addOperand(MCOperand::createImm(Imm + P)); in decodeUImmOperand()
154 Inst.addOperand(MCOperand::createImm(SignExtend64<N + S>(Imm << S))); in decodeSImmOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVAsmPrinter.cpp185 LabelInst.addOperand(MCOperand::createReg(MAI->getOrCreateMBBRegister(MBB))); in emitOpLabel()
311 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(MAI->SrcLang))); in outputDebugSourceAndStrings()
312 Inst.addOperand( in outputDebugSourceAndStrings()
323 Inst.addOperand(MCOperand::createReg(Reg)); in outputOpExtInstImports()
334 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(MAI->Addr))); in outputOpMemoryModel()
335 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(MAI->Mem))); in outputOpMemoryModel()
369 TmpInst.addOperand(MCOperand::createReg(Reg)); in outputEntryPoints()
383 Inst.addOperand(MCOperand::createImm(Cap)); in outputGlobalRequirements()
446 Inst.addOperand(MCOperand::createImm(Const->getZExtValue())); in addOpsFromMDNode()
450 Inst.addOperand(MCOperand::createReg(FuncReg)); in addOpsFromMDNode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp114 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRRegisterClass()
124 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodeFPR32RegisterClass()
134 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodesFPR32RegisterClass()
144 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodesFPR64RegisterClass()
154 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodesFPR64_VRegisterClass()
164 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodeFPR64RegisterClass()
176 Inst.addOperand(MCOperand::createReg(FPR128DecoderTable[RegNo])); in DecodesFPR128RegisterClass()
186 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodesGPRRegisterClass()
196 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodemGPRRegisterClass()
208 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRSPRegisterClass()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp132 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
175 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
185 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
187 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeRiMemoryValue()
198 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
200 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
211 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
213 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); in decodeSplsValue()
230 MI.addOperand(MCOperand::createImm(Insn)); in decodeBranch()
238 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeShiftImm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp35 NopInst.addOperand(MCOperand::createImm(0)); in getNop()
36 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop()
37 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
40 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
41 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
42 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop()
43 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
44 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h104 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
135 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
140 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
145 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
151 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
156 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
163 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
169 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
176 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
183 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp286 MI.addOperand(Imm4Op); in getInstruction()
347 Inst.addOperand(MCOperand::createReg(Register)); in DecodeSimpleRegisterClass()
362 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64x8ClassRegisterClass()
375 Inst.addOperand(MCOperand::createReg(Register)); in DecodeZPRMul2_MinMax()
389 Inst.addOperand(MCOperand::createReg(Register)); in DecodeZPR2Mul2RegisterClass()
400 Inst.addOperand(MCOperand::createReg(Register)); in DecodeZK()
411 Inst.addOperand(MCOperand::createReg(Register)); in DecodeZPR4Mul4RegisterClass()
421 Inst.addOperand(MCOperand::createImm(RegMask)); in DecodeMatrixTileListRegisterClass()
443 Inst.addOperand( in DecodeMatrixTile()
455 Inst.addOperand(MCOperand::createReg(Register)); in DecodePPR2Mul2RegisterClass()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1304 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
1318 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCLRMGPRRegisterClass()
1355 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
1370 Inst.addOperand(MCOperand::createReg(ARM::ZR)); in DecodeGPRwithZRRegisterClass()
1418 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairRegisterClass()
1429 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairnospRegisterClass()
1443 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRspRegisterClass()
1474 Inst.addOperand(MCOperand::createReg(Register)); in DecodetcGPRRegisterClass()
1511 Inst.addOperand(MCOperand::createReg(Register)); in DecodeSPRRegisterClass()
1548 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPRRegisterClass()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp387 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
392 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands()
401 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
411 Inst.addOperand(MCOperand::createExpr(NewExpr)); in addSignedImmOperands()
549 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in canonicalizeImmediates()
555 NewInst.addOperand(I); in canonicalizeImmediates()
626 MCB.addOperand(MCOperand::createImm(0)); in matchAndEmitInstruction()
659 MCB.addOperand(MCOperand::createInst(SubInst)); in matchAndEmitInstruction()
1299 TmpInst.addOperand(Rdd); in makeCombineInst()
1300 TmpInst.addOperand(MO1); in makeCombineInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp140 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
175 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9))); in DecodeMEMrs9()
193 Inst.addOperand(MCOperand::createImm(Offset)); in DecodeSymbolicOperandOff()
212 Inst.addOperand(MCOperand::createImm( in DecodeSignedOperand()
224 Inst.addOperand( in DecodeFromCyclicRange()
241 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeStLImmInstruction()
242 Inst.addOperand(MCOperand::createImm(0)); in DecodeStLImmInstruction()
259 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeLdLImmInstruction()
260 Inst.addOperand(MCOperand::createImm(0)); in DecodeLdLImmInstruction()
277 Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32))); in DecodeLdRLImmInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp1590 MCInstBuilder(AArch64::ADRP).addReg(AArch64::X17).addOperand(JTMCHi)); in LowerHardenedBRJumpTable()
1595 .addOperand(JTMCLo) in LowerHardenedBRJumpTable()
1756 MCInstBuilder(CallOpcode).addOperand(CallTargetMCOp)); in LowerSTATEPOINT()
1787 MI.addOperand(MCOperand::createReg(DefRegister)); in LowerFAULTING_OP()
1793 MI.addOperand(Dest); in LowerFAULTING_OP()
1841 MOVI.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1842 MOVI.addOperand(MCOperand::createImm(0)); in emitFMov0()
1852 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1853 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in emitFMov0()
1857 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp70 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); in decodeCondBrTarget()
78 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget()
90 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
255 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
265 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
274 Inst.addOperand(MCOperand::createImm(Imm)); in decodeImmZeroOperand()
283 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1])); in decodeVSRpEvenOperands()
291 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 2))); in decodeDispRIXOperand()
304 Inst.addOperand(MCOperand::createImm(Disp)); in decodeDispRIHashOperand()
312 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 4))); in decodeDispRIX16Operand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp189 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
198 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
199 TmpInst.addOperand(Op1); in emitRX()
219 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitII()
220 TmpInst.addOperand(MCOperand::createImm(Imm2)); in emitII()
230 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
231 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
232 TmpInst.addOperand(Op2); in emitRRX()
249 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
250 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
[all …]

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