| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 563 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
569 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
584 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
594 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
596 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
598 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
635 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 464 Inst.addOperand(MCOperand::createReg(RRegs[getRegNum()])); in addRegGPRCOperands()
469 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getRegNum()])); in addRegGPRCNoR0Operands()
474 Inst.addOperand(MCOperand::createReg(XRegs[getRegNum()])); in addRegG8RCOperands()
479 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getRegNum()])); in addRegG8RCNoX0Operands()
484 Inst.addOperand(MCOperand::createReg(XRegs[getG8pReg()])); in addRegG8pRCOperands()
503 Inst.addOperand(MCOperand::createReg(FRegs[getRegNum()])); in addRegF4RCOperands()
508 Inst.addOperand(MCOperand::createReg(FRegs[getRegNum()])); in addRegF8RCOperands()
513 Inst.addOperand(MCOperand::createReg(FpRegs[getFpReg()])); in addRegFpRCOperands()
518 Inst.addOperand(MCOperand::createReg(VFRegs[getRegNum()])); in addRegVFRCOperands()
523 Inst.addOperand(MCOperand::createReg(VRegs[getRegNum()])); in addRegVRRCOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYMCCodeEmitter.cpp | 78 .addOperand(MI.getOperand(0)) in expandJBTF()
85 .addOperand(MI.getOperand(1)) in expandJBTF()
86 .addOperand(MI.getOperand(2)); in expandJBTF()
88 TmpInst = MCInstBuilder(CSKY::JMPI32).addOperand(MI.getOperand(2)); in expandJBTF()
103 .addOperand(MI.getOperand(0)) in expandNEG()
104 .addOperand(MI.getOperand(1)); in expandNEG()
109 .addOperand(MI.getOperand(0)) in expandNEG()
110 .addOperand(MI.getOperand(0)) in expandNEG()
125 .addOperand(MI.getOperand(0)) in expandRSUBI()
126 .addOperand(M in expandRSUBI()
[all...] |
| H A D | CSKYAsmBackend.cpp | 301 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
302 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
306 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
310 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
314 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
319 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
320 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
321 Res.addOperand(Inst.getOperand(2)); in relaxInstruction()
325 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
326 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 300 ITInst.addOperand(MCOperand::createImm(ITState.Cond)); in flushPendingInstructions()
301 ITInst.addOperand(MCOperand::createImm(ITState.Mask)); in flushPendingInstructions()
2515 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
2517 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
2519 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
2534 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2536 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2541 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); in addVPTPredNOperands()
2543 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredNOperands()
2544 Inst.addOperand(MCOperand::createReg(0)); in addVPTPredNOperands()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 253 T.addOperand(Inst.getOperand(i)); in ScaleVectorOffset()
261 T.addOperand(MCOperand::createExpr(NewHE)); in ScaleVectorOffset()
285 Inst.addOperand(Reg); in HexagonProcessInstruction()
286 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
287 Inst.addOperand(S16); in HexagonProcessInstruction()
294 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
301 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
308 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
315 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
322 Inst.addOperand(MCOperand::createExpr(C255)); in HexagonProcessInstruction()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 216 CompoundInsn->addOperand(Rt); in getCompoundInsn()
217 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn()
218 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn()
228 CompoundInsn->addOperand(Rt); in getCompoundInsn()
229 CompoundInsn->addOperand(Rs); in getCompoundInsn()
230 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn()
242 CompoundInsn->addOperand(Rs); in getCompoundInsn()
243 CompoundInsn->addOperand(Rt); in getCompoundInsn()
244 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn()
255 CompoundInsn->addOperand(Rs); in getCompoundInsn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 77 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR8RegisterClass()
88 Inst.addOperand(MCOperand::createReg(Register)); in DecodeLD8RegisterClass()
148 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOARr()
164 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIORdA()
172 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOBIT()
173 Inst.addOperand(MCOperand::createImm(b)); in decodeFIOBIT()
182 Inst.addOperand(MCOperand::createImm(Field << 1)); in decodeCallTarget()
199 Inst.addOperand(MCOperand::createReg(AVR::R31R30)); in decodeFLPMX()
243 Inst.addOperand(MCOperand::createImm(k)); in decodeFWRdK()
270 Inst.addOperand( in decodeMemri()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstBuilder.h | 38 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
44 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
50 Inst.addOperand(MCOperand::createSFPImm(Val)); in addSFPImm()
56 Inst.addOperand(MCOperand::createDFPImm(Val)); in addDFPImm()
62 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
68 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
73 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
74 Inst.addOperand(Op); in addOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/Disassembler/ |
| H A D | XtensaDisassembler.cpp | 74 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeARRegisterClass()
89 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeSRRegisterClass()
109 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Imm << 2))); in decodeCallOperand()
116 Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm))); in decodeJumpOperand()
130 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm))); in decodeBranchOperand()
136 Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm))); in decodeBranchOperand()
145 Inst.addOperand(MCOperand::createImm( in decodeL32ROperand()
153 Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm))); in decodeImm8Operand()
161 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 8))); in decodeImm8_sh8Operand()
168 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm))); in decodeImm12Operand()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 89 SICInst.addOperand(RD); in emitSIC()
97 BSICInst.addOperand(R1); in emitBSIC()
98 BSICInst.addOperand(R2); in emitBSIC()
100 BSICInst.addOperand(czero); in emitBSIC()
101 BSICInst.addOperand(czero); in emitBSIC()
109 LEAInst.addOperand(RD); in emitLEAzzi()
111 LEAInst.addOperand(CZero); in emitLEAzzi()
112 LEAInst.addOperand(CZero); in emitLEAzzi()
113 LEAInst.addOperand(Imm); in emitLEAzzi()
121 LEASLInst.addOperand(RD); in emitLEASLzzi()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 80 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
91 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRX1X5RegisterClass()
102 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass()
113 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
124 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
135 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
146 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
177 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
188 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRPairRegisterClass()
199 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeSR07RegisterClass()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/Disassembler/ |
| H A D | LoongArchDisassembler.cpp | 63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); in DecodeGPRRegisterClass()
72 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo)); in DecodeFPR32RegisterClass()
81 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo)); in DecodeFPR64RegisterClass()
90 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo)); in DecodeCFRRegisterClass()
99 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo)); in DecodeFCSRRegisterClass()
108 Inst.addOperand(MCOperand::createReg(LoongArch::VR0 + RegNo)); in DecodeLSX128RegisterClass()
117 Inst.addOperand(MCOperand::createReg(LoongArch::XR0 + RegNo)); in DecodeLASX256RegisterClass()
126 Inst.addOperand(MCOperand::createReg(LoongArch::SCR0 + RegNo)); in DecodeSCRRegisterClass()
135 Inst.addOperand(MCOperand::createImm(Imm + P)); in decodeUImmOperand()
146 Inst.addOperand(MCOperand::createImm(SignExtend64<N + S>(Imm << S))); in decodeSImmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 114 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRRegisterClass()
124 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodeFPR32RegisterClass()
134 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodesFPR32RegisterClass()
144 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodesFPR64RegisterClass()
154 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodesFPR64_VRegisterClass()
164 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodeFPR64RegisterClass()
176 Inst.addOperand(MCOperand::createReg(FPR128DecoderTable[RegNo])); in DecodesFPR128RegisterClass()
186 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodesGPRRegisterClass()
196 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodemGPRRegisterClass()
208 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRSPRegisterClass()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVAsmPrinter.cpp | 159 LabelInst.addOperand(MCOperand::createReg(MAI->getOrCreateMBBRegister(MBB))); in emitOpLabel()
280 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(MAI->SrcLang))); in outputDebugSourceAndStrings()
281 Inst.addOperand( in outputDebugSourceAndStrings()
292 Inst.addOperand(MCOperand::createReg(Reg)); in outputOpExtInstImports()
303 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(MAI->Addr))); in outputOpMemoryModel()
304 Inst.addOperand(MCOperand::createImm(static_cast<unsigned>(MAI->Mem))); in outputOpMemoryModel()
338 TmpInst.addOperand(MCOperand::createReg(Reg)); in outputEntryPoints()
352 Inst.addOperand(MCOperand::createImm(Cap)); in outputGlobalRequirements()
416 Inst.addOperand(MCOperand::createImm(Const->getZExtValue())); in addOpsFromMDNode()
420 Inst.addOperand(MCOperand::createReg(FuncReg)); in addOpsFromMDNode()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
180 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
182 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeRiMemoryValue()
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
195 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
206 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
208 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); in decodeSplsValue()
225 MI.addOperand(MCOperand::createImm(Insn)); in decodeBranch()
233 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeShiftImm()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::createImm(0)); in getNop()
40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop()
41 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 279 MI.addOperand(Imm4Op); in getInstruction()
339 Inst.addOperand(MCOperand::createReg(Register)); in DecodeSimpleRegisterClass()
354 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64x8ClassRegisterClass()
365 Inst.addOperand(MCOperand::createReg(Register)); in DecodeZPR2Mul2RegisterClass()
376 Inst.addOperand(MCOperand::createReg(Register)); in DecodeZPR4Mul4RegisterClass()
386 Inst.addOperand(MCOperand::createImm(RegMask)); in DecodeMatrixTileListRegisterClass()
408 Inst.addOperand( in DecodeMatrixTile()
420 Inst.addOperand(MCOperand::createReg(Register)); in DecodePPR2Mul2RegisterClass()
429 Inst.addOperand(MCOperand::createImm(64 - Imm)); in DecodeFixedPointScaleImm32()
436 Inst.addOperand(MCOperand::createImm(64 - Imm)); in DecodeFixedPointScaleImm64()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 103 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
134 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
139 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
144 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
150 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
155 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
162 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
168 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
175 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
182 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1303 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
1317 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCLRMGPRRegisterClass()
1354 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
1369 Inst.addOperand(MCOperand::createReg(ARM::ZR)); in DecodeGPRwithZRRegisterClass()
1417 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairRegisterClass()
1428 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairnospRegisterClass()
1442 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRspRegisterClass()
1473 Inst.addOperand(MCOperand::createReg(Register)); in DecodetcGPRRegisterClass()
1510 Inst.addOperand(MCOperand::createReg(Register)); in DecodeSPRRegisterClass()
1543 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPRRegisterClass()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 385 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
390 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands()
399 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
409 Inst.addOperand(MCOperand::createExpr(NewExpr)); in addSignedImmOperands()
547 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in canonicalizeImmediates()
553 NewInst.addOperand(I); in canonicalizeImmediates()
624 MCB.addOperand(MCOperand::createImm(0)); in MatchAndEmitInstruction()
657 MCB.addOperand(MCOperand::createInst(SubInst)); in MatchAndEmitInstruction()
1292 TmpInst.addOperand(Rdd); in makeCombineInst()
1293 TmpInst.addOperand(MO1); in makeCombineInst()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 140 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
175 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9))); in DecodeMEMrs9()
193 Inst.addOperand(MCOperand::createImm(Offset)); in DecodeSymbolicOperandOff()
212 Inst.addOperand(MCOperand::createImm( in DecodeSignedOperand()
224 Inst.addOperand( in DecodeFromCyclicRange()
241 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeStLImmInstruction()
242 Inst.addOperand(MCOperand::createImm(0)); in DecodeStLImmInstruction()
259 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeLdLImmInstruction()
260 Inst.addOperand(MCOperand::createImm(0)); in DecodeLdLImmInstruction()
277 Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32))); in DecodeLdRLImmInstruction()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
188 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
189 TmpInst.addOperand(Op1); in emitRX()
208 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitII()
209 TmpInst.addOperand(MCOperand::createImm(Imm2)); in emitII()
219 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
220 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
221 TmpInst.addOperand(Op2); in emitRRX()
237 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
238 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); in decodeCondBrTarget()
76 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget()
88 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
253 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
263 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
272 Inst.addOperand(MCOperand::createImm(Imm)); in decodeImmZeroOperand()
281 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1])); in decodeVSRpEvenOperands()
289 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 2))); in decodeDispRIXOperand()
302 Inst.addOperand(MCOperand::createImm(Disp)); in decodeDispRIHashOperand()
310 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 4))); in decodeDispRIX16Operand()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 1472 MCInstBuilder(AArch64::ADRP).addReg(AArch64::X17).addOperand(JTMCHi)); in LowerHardenedBRJumpTable()
1478 .addOperand(JTMCLo) in LowerHardenedBRJumpTable()
1658 MCInstBuilder(CallOpcode).addOperand(CallTargetMCOp)); in LowerSTATEPOINT()
1689 MI.addOperand(MCOperand::createReg(DefRegister)); in LowerFAULTING_OP()
1695 MI.addOperand(Dest); in LowerFAULTING_OP()
1716 MOVI.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1717 MOVI.addOperand(MCOperand::createImm(0)); in emitFMov0()
1727 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
1728 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in emitFMov0()
1732 FMov.addOperand(MCOperand::createReg(DestReg)); in emitFMov0()
[all …]
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