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/freebsd/sys/dev/rtwn/
H A Dif_rtwnvar.h195 #define RTWN_CHIP_HAS_BCNQ1(_sc) \ argument
196 ((_sc)->bcn_status_reg[0] != (_sc)->bcn_status_reg[1])
432 #define rtwn_write_1(_sc, _addr, _val) \ argument
433 (((_sc)->sc_write_1)((_sc), (_addr), (_val)))
434 #define rtwn_write_2(_sc, _addr, _val) \ argument
435 (((_sc)->sc_write_2)((_sc), (_addr), (_val)))
436 #define rtwn_write_4(_sc, _addr, _val) \ argument
437 (((_sc)->sc_write_4)((_sc), (_addr), (_val)))
438 #define rtwn_read_1(_sc, _addr) \ argument
439 (((_sc)->sc_read_1)((_sc), (_addr)))
[all …]
/freebsd/sys/dev/wpi/
H A Dif_wpivar.h256 #define WPI_LOCK_INIT(_sc) \ argument
257 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
259 #define WPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
260 #define WPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
261 #define WPI_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
262 #define WPI_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
264 #define WPI_RXON_LOCK_INIT(_sc) \ argument
265 mtx_init(&(_sc)->rxon_mtx, "lock for wpi_rxon structure", NULL, MTX_DEF)
266 #define WPI_RXON_LOCK(_sc) mtx_lock(&(_sc)->rxon_mtx) argument
267 #define WPI_RXON_UNLOCK(_sc) mtx_unlock(&(_sc)->rxon_mtx) argument
[all …]
/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_var.h103 #define R12A_SOFTC(_sc) ((struct r12a_softc *)((_sc)->sc_priv)) argument
105 #define rtwn_r12a_fix_spur(_sc, _c) \ argument
106 ((R12A_SOFTC(_sc)->rs_fix_spur)((_sc), (_c)))
107 #define rtwn_r12a_set_band_2ghz(_sc, _rates) \ argument
108 ((R12A_SOFTC(_sc)->rs_set_band_2ghz)((_sc), (_rates)))
109 #define rtwn_r12a_set_band_5ghz(_sc, _rates) \ argument
110 ((R12A_SOFTC(_sc)->rs_set_band_5ghz)((_sc), (_rates)))
111 #define rtwn_r12a_init_burstlen(_sc) \ argument
112 ((R12A_SOFTC(_sc)->rs_init_burstlen)((_sc)))
113 #define rtwn_r12a_init_ampdu_fwhw(_sc) \ argument
[all …]
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_private.h34 #define BHND_PMU_READ_4(_sc, _reg) (_sc)->io->rd4((_reg), (_sc)->io_ctx) argument
35 #define BHND_PMU_WRITE_4(_sc, _reg, _val) \ argument
36 (_sc)->io->wr4((_reg), (_val), (_sc)->io_ctx)
38 #define BHND_PMU_AND_4(_sc, _reg, _val) \ argument
39 BHND_PMU_WRITE_4((_sc), (_reg), \
40 BHND_PMU_READ_4((_sc), (_reg)) & (_val))
41 #define BHND_PMU_OR_4(_sc, _reg, _val) \ argument
42 BHND_PMU_WRITE_4((_sc), (_reg), \
43 BHND_PMU_READ_4((_sc), (_reg)) | (_val))
46 #define BHND_PMU_IND_READ(_sc, _src, _reg) \ argument
[all …]
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_common.h29 #define READ4(_sc, _reg) \ argument
30 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
31 #define WRITE4(_sc, _reg, _val) \ argument
32 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
33 #define READ2(_sc, _reg) \ argument
34 bus_space_read_2(_sc->bst, _sc->bsh, _reg)
35 #define WRITE2(_sc, _reg, _val) \ argument
36 bus_space_write_2(_sc->bst, _sc->bsh, _reg, _val)
37 #define READ1(_sc, _reg) \ argument
38 bus_space_read_1(_sc->bst, _sc->bsh, _reg)
[all …]
H A Dvf_edma.h111 #define TCD_READ4(_sc, _reg) \ argument
112 bus_space_read_4(_sc->bst_tcd, _sc->bsh_tcd, _reg)
113 #define TCD_WRITE4(_sc, _reg, _val) \ argument
114 bus_space_write_4(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
115 #define TCD_READ2(_sc, _reg) \ argument
116 bus_space_read_2(_sc->bst_tcd, _sc->bsh_tcd, _reg)
117 #define TCD_WRITE2(_sc, _reg, _val) \ argument
118 bus_space_write_2(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
119 #define TCD_READ1(_sc, _reg) \ argument
120 bus_space_read_1(_sc->bst_tcd, _sc->bsh_tcd, _reg)
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_var.h65 #define R92C_SOFTC(_sc) ((struct r92c_softc *)((_sc)->sc_priv)) argument
67 #define rtwn_r92c_set_bw20(_sc, _chan) \ argument
68 ((R92C_SOFTC(_sc)->rs_set_bw20)((_sc), (_chan)))
69 #define rtwn_r92c_get_txpower(_sc, _chain, _c, _power) \ argument
70 ((R92C_SOFTC(_sc)->rs_get_txpower)((_sc), (_chain), (_c), (_power)))
71 #define rtwn_r92c_set_gain(_sc, _gain) \ argument
72 ((R92C_SOFTC(_sc)->rs_set_gain)((_sc), (_gain)))
73 #define rtwn_r92c_tx_enable_ampdu(_sc, _buf, _enable) \ argument
74 ((R92C_SOFTC(_sc)->rs_tx_enable_ampdu)((_buf), (_enable)))
75 #define rtwn_r92c_tx_setup_hwseq(_sc, _buf) \ argument
[all …]
/freebsd/sys/fs/p9fs/
H A Dp9fs.h77 #define P9FS_VFID_MTX(_sc) (&(_sc)->vfid_mtx) argument
78 #define P9FS_VFID_LOCK(_sc) mtx_lock(P9FS_VFID_MTX(_sc)) argument
79 #define P9FS_VFID_UNLOCK(_sc) mtx_unlock(P9FS_VFID_MTX(_sc)) argument
80 #define P9FS_VFID_LOCK_INIT(_sc) mtx_init(P9FS_VFID_MTX(_sc), \ argument
82 #define P9FS_VFID_LOCK_DESTROY(_sc) mtx_destroy(P9FS_VFID_MTX(_sc)) argument
84 #define P9FS_VOFID_MTX(_sc) (&(_sc)->vofid_mtx) argument
85 #define P9FS_VOFID_LOCK(_sc) mtx_lock(P9FS_VOFID_MTX(_sc)) argument
86 #define P9FS_VOFID_UNLOCK(_sc) mtx_unlock(P9FS_VOFID_MTX(_sc)) argument
87 #define P9FS_VOFID_LOCK_INIT(_sc) mtx_init(P9FS_VOFID_MTX(_sc), \ argument
89 #define P9FS_VOFID_LOCK_DESTROY(_sc) mtx_destroy(P9FS_VOFID_MTX(_sc)) argument
[all …]
/freebsd/sys/dev/ath/
H A Dif_ath_rx.h39 #define ath_stoprecv(_sc, _dodelay) \ argument
40 (_sc)->sc_rx.recv_stop((_sc), (_dodelay))
41 #define ath_startrecv(_sc) \ argument
42 (_sc)->sc_rx.recv_start((_sc))
43 #define ath_rx_flush(_sc) \ argument
44 (_sc)->sc_rx.recv_flush((_sc))
45 #define ath_rxbuf_init(_sc, _bf) \ argument
46 (_sc)->sc_rx.recv_rxbuf_init((_sc), (_bf))
47 #define ath_rxdma_setup(_sc) \ argument
48 (_sc)->sc_rx.recv_setup(_sc)
[all …]
H A Dif_athvar.h401 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ argument
403 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
933 #define ATH_LOCK_INIT(_sc) \ argument
934 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
936 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
937 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
938 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
939 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
940 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) argument
946 #define ATH_TX_LOCK_INIT(_sc) do {\ argument
[all …]
H A Dif_ath_tx.h154 #define ath_txdma_setup(_sc) \ argument
155 (_sc)->sc_tx.xmit_setup(_sc)
156 #define ath_txdma_teardown(_sc) \ argument
157 (_sc)->sc_tx.xmit_teardown(_sc)
158 #define ath_txq_restart_dma(_sc, _txq) \ argument
159 (_sc)->sc_tx.xmit_dma_restart((_sc), (_txq))
160 #define ath_tx_handoff(_sc, _txq, _bf) \ argument
161 (_sc)->sc_tx.xmit_handoff((_sc), (_txq), (_bf))
162 #define ath_draintxq(_sc, _rtype) \ argument
163 (_sc)->sc_tx.xmit_drain((_sc), (_rtype))
/freebsd/sys/arm/ti/
H A Dti_adcvar.h32 #define ADC_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg) argument
33 #define ADC_WRITE4(_sc, reg, value) \ argument
34 bus_write_4((_sc)->sc_mem_res, reg, value)
73 #define TI_ADC_LOCK(_sc) \ argument
74 mtx_lock(&(_sc)->sc_mtx)
75 #define TI_ADC_UNLOCK(_sc) \ argument
76 mtx_unlock(&(_sc)->sc_mtx)
77 #define TI_ADC_LOCK_INIT(_sc) \ argument
78 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
80 #define TI_ADC_LOCK_DESTROY(_sc) \ argument
[all …]
H A Dti_spivar.h59 #define TI_SPI_WRITE(_sc, _off, _val) \ argument
60 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val))
61 #define TI_SPI_READ(_sc, _off) \ argument
62 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off))
64 #define TI_SPI_LOCK(_sc) \ argument
65 mtx_lock(&(_sc)->sc_mtx)
66 #define TI_SPI_UNLOCK(_sc) \ argument
67 mtx_unlock(&(_sc)->sc_mtx)
/freebsd/sys/dev/mwl/
H A Dif_mwlvar.h131 #define MWL_TXQ_LOCK_INIT(_sc, _tq) do { \ argument
133 device_get_nameunit((_sc)->sc_dev), (_tq)->qnum); \
155 #define MWL_JUMBO_OFFSET(_sc, _data) \ argument
156 (((const uint8_t *)(_data)) - (const uint8_t *)((_sc)->sc_rxmem))
157 #define MWL_JUMBO_DMA_ADDR(_sc, _data) \ argument
158 ((_sc)->sc_rxmem_paddr + MWL_JUMBO_OFFSET(_sc, _data))
341 #define MWL_LOCK_INIT(_sc) \ argument
342 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
344 #define MWL_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
345 #define MWL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
[all …]
/freebsd/sys/arm/altera/socfpga/
H A Dsocfpga_common.h31 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) argument
32 #define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) argument
33 #define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) argument
34 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) argument
35 #define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) argument
36 #define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val) argument
/freebsd/sys/dev/age/
H A Dif_agevar.h237 #define CSR_WRITE_4(_sc, reg, val) \ argument
238 bus_write_4((_sc)->age_res[0], (reg), (val))
239 #define CSR_WRITE_2(_sc, reg, val) \ argument
240 bus_write_2((_sc)->age_res[0], (reg), (val))
241 #define CSR_READ_2(_sc, reg) \ argument
242 bus_read_2((_sc)->age_res[0], (reg))
243 #define CSR_READ_4(_sc, reg) \ argument
244 bus_read_4((_sc)->age_res[0], (reg))
246 #define AGE_LOCK(_sc) mtx_lock(&(_sc)->age_mtx) argument
247 #define AGE_UNLOCK(_sc) mtx_unlock(&(_sc)->age_mtx) argument
[all …]
/freebsd/sys/dev/etherswitch/mtkswitch/
H A Dmtkswitchvar.h40 #define MTK_IS_SWITCH(_sc, _type) \ argument
41 (!!((_sc)->sc_switchtype == MTK_SWITCH_ ## _type))
119 #define MTKSWITCH_LOCK(_sc) \ argument
120 mtx_lock(&(_sc)->sc_mtx)
121 #define MTKSWITCH_UNLOCK(_sc) \ argument
122 mtx_unlock(&(_sc)->sc_mtx)
123 #define MTKSWITCH_LOCK_ASSERT(_sc, _what) \ argument
124 mtx_assert(&(_sc)->sc_mtx, (_what))
125 #define MTKSWITCH_TRYLOCK(_sc) \ argument
126 mtx_trylock(&(_sc)->sc_mtx)
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_pwm.c72 #define BCM_PWM_MEM_WRITE(_sc, _off, _val) \ argument
73 bus_space_write_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off, _val)
74 #define BCM_PWM_MEM_READ(_sc, _off) \ argument
75 bus_space_read_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off)
76 #define BCM_PWM_CLK_WRITE(_sc, _off, _val) \ argument
77 bus_space_write_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off, _val)
78 #define BCM_PWM_CLK_READ(_sc, _off) \ argument
79 bus_space_read_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off)
81 #define W_CTL(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x00, _val) argument
82 #define R_CTL(_sc) BCM_PWM_MEM_READ(_sc, 0x00) argument
[all …]
H A Dbcm2835_spivar.h52 #define BCM_SPI_WRITE(_sc, _off, _val) \ argument
53 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
54 #define BCM_SPI_READ(_sc, _off) \ argument
55 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
57 #define BCM_SPI_LOCK(_sc) \ argument
58 mtx_lock(&(_sc)->sc_mtx)
59 #define BCM_SPI_UNLOCK(_sc) \ argument
60 mtx_unlock(&(_sc)->sc_mtx)
H A Dbcm2835_bscvar.h59 #define BCM_BSC_WRITE(_sc, _off, _val) \ argument
60 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
61 #define BCM_BSC_READ(_sc, _off) \ argument
62 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
64 #define BCM_BSC_LOCK(_sc) \ argument
65 mtx_lock(&(_sc)->sc_mtx)
66 #define BCM_BSC_UNLOCK(_sc) \ argument
67 mtx_unlock(&(_sc)->sc_mtx)
/freebsd/sys/arm/ti/am335x/
H A Dam335x_ecap.c57 #define ECAP_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg); argument
58 #define ECAP_WRITE2(_sc, reg, value) \ argument
59 bus_write_2((_sc)->sc_mem_res, reg, value);
60 #define ECAP_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); argument
61 #define ECAP_WRITE4(_sc, reg, value) \ argument
62 bus_write_4((_sc)->sc_mem_res, reg, value);
64 #define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
65 #define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
66 #define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ argument
67 device_get_nameunit(_sc->sc_dev), "am335x_ecap softc", MTX_DEF)
[all …]
/freebsd/sys/dev/virtio/scsi/
H A Dvirtio_scsivar.h144 #define VTSCSI_MTX(_sc) &(_sc)->vtscsi_mtx argument
145 #define VTSCSI_LOCK_INIT(_sc, _name) mtx_init(VTSCSI_MTX(_sc), _name, \ argument
147 #define VTSCSI_LOCK(_sc) mtx_lock(VTSCSI_MTX(_sc)) argument
148 #define VTSCSI_UNLOCK(_sc) mtx_unlock(VTSCSI_MTX(_sc)) argument
149 #define VTSCSI_LOCK_OWNED(_sc) mtx_assert(VTSCSI_MTX(_sc), MA_OWNED) argument
150 #define VTSCSI_LOCK_NOTOWNED(_sc) mtx_assert(VTSCSI_MTX(_sc), MA_NOTOWNED) argument
151 #define VTSCSI_LOCK_DESTROY(_sc) mtx_destroy(VTSCSI_MTX(_sc)) argument
172 #define vtscsi_dprintf(_sc, _level, _msg, _args ...) do { \ argument
173 if ((_sc)->vtscsi_debug & (_level)) \
174 device_printf((_sc)->vtscsi_dev, "%s: "_msg, \
/freebsd/sys/dev/alc/
H A Dif_alcvar.h260 #define CSR_WRITE_4(_sc, reg, val) \ argument
261 bus_write_4((_sc)->alc_res[0], (reg), (val))
262 #define CSR_WRITE_2(_sc, reg, val) \ argument
263 bus_write_2((_sc)->alc_res[0], (reg), (val))
264 #define CSR_WRITE_1(_sc, reg, val) \ argument
265 bus_write_1((_sc)->alc_res[0], (reg), (val))
266 #define CSR_READ_2(_sc, reg) \ argument
267 bus_read_2((_sc)->alc_res[0], (reg))
268 #define CSR_READ_4(_sc, reg) \ argument
269 bus_read_4((_sc)->alc_res[0], (reg))
[all …]
/freebsd/sys/dev/stge/
H A Dif_stgereg.h89 #define CSR_WRITE_4(_sc, reg, val) \ argument
90 bus_write_4((_sc)->sc_res[0], (reg), (val))
91 #define CSR_WRITE_2(_sc, reg, val) \ argument
92 bus_write_2((_sc)->sc_res[0], (reg), (val))
93 #define CSR_WRITE_1(_sc, reg, val) \ argument
94 bus_write_1((_sc)->sc_res[0], (reg), (val))
96 #define CSR_READ_4(_sc, reg) \ argument
97 bus_read_4((_sc)->sc_res[0], (reg))
98 #define CSR_READ_2(_sc, reg) \ argument
99 bus_read_2((_sc)->sc_res[0], (reg))
[all …]
/freebsd/sys/dev/etherswitch/e6000sw/
H A De6000swreg.h51 #define MVSWITCH(_sc, id) ((_sc)->swid == (id)) argument
52 #define MVSWITCH_MULTICHIP(_sc) ((_sc)->sw_addr != 0) argument
59 #define REG_PORT(_sc, p) ((MVSWITCH((_sc), MV88E6190) ? 0 : 0x10) + (p)) argument
104 #define PORT_MASK(_sc) 0x7f argument
141 #define VTU_FID_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff : 0xff) argument
147 #define VTU_PPREG(_sc) (MVSWITCH((_sc), MV88E6190) ? 8 : 4) argument
148 #define VTU_PORT(_sc, p) (((p) % VTU_PPREG(_sc)) * (16 / VTU_PPREG(_sc))) argument
177 #define ATU_PORT_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff0 : 0xff0) argument

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