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/freebsd/contrib/bc/tests/dc/
H A Dboolean.txt4 _1 1(pR
5 _1 0(pR
6 _1 _1(pR
7 _1 _2(pR
11 _1 1{pR
12 _1 0{pR
13 _1 _1{pR
14 _1 _2{pR
18 _1 1)pR
19 _1 0)pR
[all …]
H A Dpower.txt17 1 _1^pR
18 2 _1^pR
19 10 _1^pR
20 683734768 _1^pR
21 38579623756.897937568235 _1^pR
25 _1 1^pR
26 _1 2^pR
34 _1 _1^pR
35 _1 _2^pR
36 _2 _1^pR
H A Dmodulus.txt11 _1 1%pR
16 1 _1%pR
17 2 _1%pR
25 _1 _1%pR
26 _2 _1%pR
44 _1 1%pR
49 1 _1%pR
50 2 _1%pR
58 _1 _1%pR
59 _2 _1%pR
H A Dshift.txt23 _1 0HpR
26 _1.298346 0HpR
29 _1.298346 4HpR
33 _1 0hpR
36 _1.298346 0hpR
39 _1.298346 4hpR
/freebsd/contrib/atf/atf-c/
H A Dmacros_test.c419 H_CHECK_EQ(1_1, 1, 1);
421 H_CHECK_EQ(2_1, 2, 1);
423 H_CHECK_EQ_MSG(1_1, 1, 1, "1 does not match 1");
425 H_CHECK_EQ_MSG(2_1, 2, 1, "2 does not match 1");
437 { H_CHECK_EQ_HEAD_NAME(1_1), H_CHECK_EQ_BODY_NAME(1_1), in ATF_TC_BODY()
441 { H_CHECK_EQ_HEAD_NAME(2_1), H_CHECK_EQ_BODY_NAME(2_1), in ATF_TC_BODY()
445 { H_CHECK_EQ_MSG_HEAD_NAME(1_1), H_CHECK_EQ_MSG_BODY_NAME(1_1), in ATF_TC_BODY()
449 { H_CHECK_EQ_MSG_HEAD_NAME(2_1), H_CHECK_EQ_MSG_BODY_NAME(2_1), in ATF_TC_BODY()
458 H_CHECK_STREQ(1_1, "1", "1");
460 H_CHECK_STREQ(2_1, "2", "1");
[all …]
/freebsd/contrib/gdtoa/
H A Dstrtordd.c50 L[_1] = (bits[1] >> 21 | bits[2] << 11) & (ULong)0xffffffffL;
88 L[2+_1] = bits[0];
101 L[_1] = bits[0];
110 L[_1] = (bits[2] << i | bits[1] >> j) & 0xffffffffL;
112 L[2+_1] = bits[0];
121 L[_1] = (bits[2] << i | bits[1] >> j) & 0xffffffffL;
123 L[2+_1] = bits[0];
128 L[_1] = bits[1];
130 L[2+_1] = bits[0];
136 L[_1] = (bits[1] << i | bits[0] >> j) & 0xffffffffL;
[all …]
H A Dstrtopdd.c69 u->L[_1] = (bits[1] >> 21 | bits[2] << 11) & 0xffffffffL;
107 u->L[2+_1] = bits[0];
120 u->L[_1] = bits[0];
129 u->L[_1] = (bits[2] << i | bits[1] >> j) & 0xffffffffL;
131 u->L[2+_1] = bits[0];
140 u->L[_1] = ((bits[2] << i) | (bits[1] >> j)) & 0xffffffffL;
142 u->L[2+_1] = bits[0];
147 u->L[_1] = bits[1];
149 u->L[2+_1] = bits[0];
155 u->L[_1] = (bits[1] << i | bits[0] >> j) & 0xffffffffL;
[all …]
H A DstrtorQ.c37 #undef _1
43 #define _1 1 macro
49 #define _1 2 macro
70 L[_1] = bits[2];
77 L[_1] = bits[2];
85 L[_1] = bits[2];
91 L[_1] = L[_2] = L[_3] = 0;
H A DstrtopQ.c35 #undef _1
41 #define _1 1 macro
47 #define _1 2 macro
81 L[_1] = bits[2];
88 L[_1] = bits[2];
94 L[_1] = L[_2] = L[_3] = 0;
H A DstrtopxL.c35 #undef _1
41 #define _1 1 macro
46 #define _1 1 macro
79 L[_1] = bits[1];
85 L[_1] = 0x80000000;
H A Dstrtorx.c37 #undef _1
43 #define _1 1 macro
50 #define _1 3 macro
79 L[_1] = (UShort)(bits[1] >> 16);
87 L[_1] = (UShort)((bits[1] >> 16) | (3 << 14));
92 L[_1] = 0x8000;
H A Dstrtopx.c35 #undef _1
41 #define _1 1 macro
48 #define _1 3 macro
90 L[_1] = (UShort)(bits[1] >> 16);
95 L[_1] = 0x8000;
H A DstrtorxL.c35 #undef _1
41 #define _1 1 macro
46 #define _1 1 macro
67 L[_1] = bits[1];
73 L[_1] = 0x80000000;
H A Dstrtodnrp.c61 u.L[_1] = bits[0];
66 u.L[_1] = bits[0];
72 u.L[_1] = 0;
82 u.L[_1] = bits[0];
H A Dg_xLfmt.c35 #undef _1
41 #define _1 1 macro
46 #define _1 1 macro
74 bits[1] = L[_1];
/freebsd/contrib/bc/tests/dc/errors/
H A D13.txt2 _1 _1(pR
3 _1 _2(pR
5 _1 1{pR 999+pR
14 _1 _1+pR
H A D32.txt6 _1 0{pR
7 _1 _1{pR
8 _1 f0070000000000.0000000000000_10000000000006.00000000000005|pRpR
H A D17.txt6 _1 0{pR
7 _1 _1{pR
8 _1 f2872917389671.7573280963748_13784962873546.09287293954765~pRpR
/freebsd/contrib/googletest/googlemock/include/gmock/internal/
H A Dgmock-pp.h5 #define GMOCK_PP_CAT(_1, _2) GMOCK_PP_INTERNAL_CAT(_1, _2) argument
17 #define GMOCK_PP_IDENTITY(_1) _1 argument
152 #define GMOCK_PP_INTERNAL_CAT(_1, _2) _1##_2 argument
154 #define GMOCK_PP_INTERNAL_CAT_5(_1, _2, _3, _4, _5) _1##_2##_3##_4##_5 argument
155 #define GMOCK_PP_INTERNAL_IS_EMPTY(_1, _2, _3, _4) \ argument
157 _1, _2, _3, _4))
167 #define GMOCK_PP_INTERNAL_INTERNAL_16TH(_1, _2, _3, _4, _5, _6, _7, _8, _9, \ argument
173 #define GMOCK_PP_INTERNAL_INTERNAL_HEAD(_1, ...) _1 argument
176 #define GMOCK_PP_INTERNAL_INTERNAL_TAIL(_1, ...) __VA_ARGS__ argument
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dvdev_raidz_math_aarch64_neon_common.h32 #define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N argument
36 #define VR1_(_1, REG, ...) "%[w"#REG"]" argument
37 #define VR2_(_1, _2, REG, ...) "%[w"#REG"]" argument
38 #define VR3_(_1, _2, _3, REG, ...) "%[w"#REG"]" argument
39 #define VR4_(_1, _2, _3, _4, REG, ...) "%[w"#REG"]" argument
40 #define VR5_(_1, _2, _3, _4, _5, REG, ...) "%[w"#REG"]" argument
41 #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "%[w"#REG"]" argument
42 #define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "%[w"#REG"]" argument
65 #define RVR1_(_1, REG, ...) [w##REG] "w" (w##REG) argument
66 #define RVR2_(_1, _2, REG, ...) [w##REG] "w" (w##REG) argument
[all …]
H A Dvdev_raidz_math_powerpc_altivec_common.h29 #define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N argument
33 #define VR1_(_1, REG, ...) "%[w"#REG"]" argument
34 #define VR2_(_1, _2, REG, ...) "%[w"#REG"]" argument
35 #define VR3_(_1, _2, _3, REG, ...) "%[w"#REG"]" argument
36 #define VR4_(_1, _2, _3, _4, REG, ...) "%[w"#REG"]" argument
37 #define VR5_(_1, _2, _3, _4, _5, REG, ...) "%[w"#REG"]" argument
38 #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "%[w"#REG"]" argument
39 #define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "%[w"#REG"]" argument
62 #define RVR1_(_1, REG, ...) [w##REG] "v" (w##REG) argument
63 #define RVR2_(_1, _2, REG, ...) [w##REG] "v" (w##REG) argument
[all …]
H A Dvdev_raidz_math_avx512f.c38 #define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N argument
42 #define VR1_(_1, REG, ...) "zmm"#REG argument
43 #define VR2_(_1, _2, REG, ...) "zmm"#REG argument
44 #define VR3_(_1, _2, _3, REG, ...) "zmm"#REG argument
45 #define VR4_(_1, _2, _3, _4, REG, ...) "zmm"#REG argument
46 #define VR5_(_1, _2, _3, _4, _5, REG, ...) "zmm"#REG argument
47 #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "zmm"#REG argument
48 #define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "zmm"#REG argument
60 #define VRy1_(_1, REG, ...) "ymm"#REG argument
61 #define VRy2_(_1, _2, REG, ...) "ymm"#REG argument
[all …]
H A Dvdev_raidz_math_ssse3.c36 #define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N argument
40 #define VR1_(_1, REG, ...) "xmm"#REG argument
41 #define VR2_(_1, _2, REG, ...) "xmm"#REG argument
42 #define VR3_(_1, _2, _3, REG, ...) "xmm"#REG argument
43 #define VR4_(_1, _2, _3, _4, REG, ...) "xmm"#REG argument
44 #define VR5_(_1, _2, _3, _4, _5, REG, ...) "xmm"#REG argument
45 #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "xmm"#REG argument
46 #define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "xmm"#REG argument
58 #define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3 argument
H A Dvdev_raidz_math_avx2.c35 #define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N argument
39 #define VR1_(_1, REG, ...) "ymm"#REG argument
40 #define VR2_(_1, _2, REG, ...) "ymm"#REG argument
41 #define VR3_(_1, _2, _3, REG, ...) "ymm"#REG argument
42 #define VR4_(_1, _2, _3, _4, REG, ...) "ymm"#REG argument
43 #define VR5_(_1, _2, _3, _4, _5, REG, ...) "ymm"#REG argument
44 #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "ymm"#REG argument
45 #define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "ymm"#REG argument
57 #define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3 argument
H A Dvdev_raidz_math_avx512bw.c39 #define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N argument
43 #define VR1_(_1, REG, ...) "zmm"#REG argument
44 #define VR2_(_1, _2, REG, ...) "zmm"#REG argument
45 #define VR3_(_1, _2, _3, REG, ...) "zmm"#REG argument
46 #define VR4_(_1, _2, _3, _4, REG, ...) "zmm"#REG argument
47 #define VR5_(_1, _2, _3, _4, _5, REG, ...) "zmm"#REG argument
48 #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "zmm"#REG argument
49 #define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "zmm"#REG argument
61 #define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3 argument

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