| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 441 SDValue ZeroVec = in getMaskBroadcast() local
448 return DAG.getSetCC(DL, BoolVecTy, BCVec, ZeroVec, ISD::CondCode::SETNE); in getMaskBroadcast()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 430 Register ZeroVec = B.buildConstant(HalfTy, 0).getReg(0); in applyCombineMulCMLT() local
434 B.buildICmp(CmpInst::Predicate::ICMP_SLT, HalfTy, CastReg, ZeroVec) in applyCombineMulCMLT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 61 Constant *ZeroVec = Constant::getNullValue(II.getType()); in simplifyX86MaskedLoad() local
65 return IC.replaceInstUsesWith(II, ZeroVec); in simplifyX86MaskedLoad()
72 II.getType(), Ptr, Align(1), BoolMask, ZeroVec); in simplifyX86MaskedLoad()
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| H A D | X86ISelLowering.cpp | 20918 SDValue ZeroVec = DAG.getConstant(0, dl, InVT); in LowerAVXExtend() local
20921 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); in LowerAVXExtend()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 2552 llvm::Value *ZeroVec = llvm::Constant::getNullValue(ScalableSrcTy); in VisitCastExpr() local
2553 Src = Builder.CreateInsertVector(ScalableSrcTy, ZeroVec, Src, in VisitCastExpr()
5604 llvm::Value *ZeroVec = llvm::Constant::getNullValue(VecTy); in VisitAbstractConditionalOperator() local
5606 CondV = Builder.CreateICmpNE(CondV, ZeroVec, "vector_cond"); in VisitAbstractConditionalOperator()
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| H A D | CGCall.cpp | 1494 llvm::Value *ZeroVec = llvm::Constant::getNullValue(FromTy); in CoerceScalableToFixed() local
1495 V = CGF.Builder.CreateInsertVector(FromTy, ZeroVec, V, uint64_t(0)); in CoerceScalableToFixed()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 6637 SDValue ZeroVec = in lowerZERO_EXTEND_VECTOR_INREG() local
6649 SDValue Shuf = DAG.getVectorShuffle(InVT, DL, PackedOp, ZeroVec, Mask); in lowerZERO_EXTEND_VECTOR_INREG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10324 SDValue ZeroVec = DAG.getNode(ARMISD::VMOVIMM, dl, VT, in LowerMLOAD() local
10327 VT, dl, N->getChain(), N->getBasePtr(), N->getOffset(), Mask, ZeroVec, in LowerMLOAD()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 24346 SDValue ZeroVec = DAG.getConstant(0, DL, VecVT); in reduceBuildVecToShuffleWithZero() local
24349 ZeroVec, ShufMask, DAG); in reduceBuildVecToShuffleWithZero()
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