Searched refs:ZeroSplat (Results 1 – 4 of 4) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVLegalizerInfo.cpp | 759 auto ZeroSplat = in legalizeSplatVector() local 761 MIB.buildICmp(CmpInst::Predicate::ICMP_NE, Dst, LHS, ZeroSplat); in legalizeSplatVector()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstCombineIntrinsic.cpp | 245 SmallVector<int, 16> ZeroSplat(VWidth, 0); in simplifyX86immShift() local 246 Amt = Builder.CreateShuffleVector(Amt, ZeroSplat); in simplifyX86immShift()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 11310 SDValue ZeroSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT, in lowerVPExtMaskOp() 11319 ZeroSplat, DAG.getUNDEF(ContainerVT), VL); in lowerVPExtMaskOp() 11441 SDValue ZeroSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT, in lowerVPFPIntConvOp() 11448 ZeroSplat, DAG.getUNDEF(IntVT), VL); in lowerVPFPIntConvOp() 11308 SDValue ZeroSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerVT, lowerVPExtMaskOp() local 11439 SDValue ZeroSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT, lowerVPFPIntConvOp() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 19076 APInt ZeroSplat(VT.getSizeInBits(), 0); in performANDCombine() local 19078 ZeroSplat |= Known.Zero.zext(VT.getSizeInBits()) in performANDCombine() 19081 DefBits = ~(DefBits | ZeroSplat); in performANDCombine() 19088 UndefBits = ~(UndefBits | ZeroSplat); in performANDCombine()
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