Searched refs:ZeroRHS (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 3426 APInt UndefRHS, ZeroRHS; in SimplifyDemandedVectorElts() local
3430 if (SimplifyDemandedVectorElts(RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3435 KnownZero = ZeroLHS & ZeroRHS; in SimplifyDemandedVectorElts()
3468 APInt UndefRHS, ZeroRHS; in SimplifyDemandedVectorElts() local
3472 if (SimplifyDemandedVectorElts(RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3515 if (ZeroRHS[M - NumElts]) in SimplifyDemandedVectorElts()
3597 APInt UndefRHS, ZeroRHS; in SimplifyDemandedVectorElts() local
3598 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3606 KnownZero = ZeroLHS & ZeroRHS; in SimplifyDemandedVectorElts()
3624 APInt UndefRHS, ZeroRHS; in SimplifyDemandedVectorElts() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 46134 bool ZeroRHS = ISD::isBuildVectorAllZeros(RHS.getNode()); in combineSelect() local
46136 if ((SelectableLHS && ZeroRHS) || (SelectableRHS && ZeroLHS)) { in combineSelect()
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