Searched refs:Zdn (Results 1 – 4 of 4) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | SVEInstrFormats.td | 990 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, pprty:$Pm), 991 asm, "\t$Zdn, $Pm", 995 bits<5> Zdn; 1003 let Inst{4-0} = Zdn; 1005 let Constraints = "$Zdn = $_Zdn"; 1021 def : InstAlias<asm # "\t$Zdn, $Pm", 1022 (!cast<Instruction>(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>; 1023 def : InstAlias<asm # "\t$Zdn, $Pm", 1024 (!cast<Instruction>(NAME # "_S") ZPR32:$Zdn, PPRAny:$Pm), 0>; 1025 def : InstAlias<asm # "\t$Zdn, $Pm", [all …]
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H A D | SMEInstrFormats.td | 1657 : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm), 1658 mnemonic, "\t$Zdn, $_Zdn, $Zm", 1661 bits<4> Zdn; 1668 let Inst{4-1} = Zdn; 1671 let Constraints = "$Zdn = $_Zdn"; 1697 : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm), 1698 mnemonic, "\t$Zdn, $_Zdn, $Zm", 1701 bits<3> Zdn; 1708 let Inst{4-2} = Zdn; 1712 let Constraints = "$Zdn = $_Zdn"; [all …]
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H A D | AArch64ISelDAGToDAG.cpp | 1893 SDValue Zdn = GetMultiVecOperand(FirstVecIdx); in SelectDestructiveMultiIntrinsic() local 1904 N->getOperand(1), Zdn, Zm); in SelectDestructiveMultiIntrinsic() 1906 Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, Zdn, Zm); in SelectDestructiveMultiIntrinsic()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 1626 unsigned Zdn = fieldFromInstruction(insn, 0, 5); in DecodeSVELogicalImmInstruction() local 1632 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr, in DecodeSVELogicalImmInstruction() 1635 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr, in DecodeSVELogicalImmInstruction()
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