1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Thomas Skibo
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * A GPIO driver for Xilinx Zynq-7000.
31 *
32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
33 *
34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are
35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of
36 * Zynq as EMIO signals.
37 *
38 * The hardware provides a way to use IOs as interrupt sources but the
39 * gpio framework doesn't seem to have hooks for this.
40 *
41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
42 * (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in
43 * chater 14. Register definitions are in appendix B.19.
44 */
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/conf.h>
49 #include <sys/bus.h>
50 #include <sys/kernel.h>
51 #include <sys/module.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/resource.h>
55 #include <sys/rman.h>
56 #include <sys/gpio.h>
57
58 #include <machine/bus.h>
59 #include <machine/resource.h>
60 #include <machine/stdarg.h>
61
62 #include <dev/gpio/gpiobusvar.h>
63 #include <dev/ofw/ofw_bus.h>
64 #include <dev/ofw/ofw_bus_subr.h>
65
66 #include "gpio_if.h"
67
68 #define ZYNQ7_MAX_BANK 4
69 #define ZYNQMP_MAX_BANK 6
70
71 /* Zynq 7000 */
72 #define ZYNQ7_BANK0_PIN_MIN 0
73 #define ZYNQ7_BANK0_NPIN 32
74 #define ZYNQ7_BANK1_PIN_MIN 32
75 #define ZYNQ7_BANK1_NPIN 22
76 #define ZYNQ7_BANK2_PIN_MIN 64
77 #define ZYNQ7_BANK2_NPIN 32
78 #define ZYNQ7_BANK3_PIN_MIN 96
79 #define ZYNQ7_BANK3_NPIN 32
80 #define ZYNQ7_PIN_MIO_MIN 0
81 #define ZYNQ7_PIN_MIO_MAX 54
82 #define ZYNQ7_PIN_EMIO_MIN 64
83 #define ZYNQ7_PIN_EMIO_MAX 118
84
85 /* ZynqMP */
86 #define ZYNQMP_BANK0_PIN_MIN 0
87 #define ZYNQMP_BANK0_NPIN 26
88 #define ZYNQMP_BANK1_PIN_MIN 26
89 #define ZYNQMP_BANK1_NPIN 26
90 #define ZYNQMP_BANK2_PIN_MIN 52
91 #define ZYNQMP_BANK2_NPIN 26
92 #define ZYNQMP_BANK3_PIN_MIN 78
93 #define ZYNQMP_BANK3_NPIN 32
94 #define ZYNQMP_BANK4_PIN_MIN 110
95 #define ZYNQMP_BANK4_NPIN 32
96 #define ZYNQMP_BANK5_PIN_MIN 142
97 #define ZYNQMP_BANK5_NPIN 32
98 #define ZYNQMP_PIN_MIO_MIN 0
99 #define ZYNQMP_PIN_MIO_MAX 77
100 #define ZYNQMP_PIN_EMIO_MIN 78
101 #define ZYNQMP_PIN_EMIO_MAX 174
102
103 #define ZYNQ_BANK_NPIN(type, bank) (ZYNQ##type##_BANK##bank##_NPIN)
104 #define ZYNQ_BANK_PIN_MIN(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN)
105 #define ZYNQ_BANK_PIN_MAX(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN + ZYNQ##type##_BANK##bank##_NPIN - 1)
106
107 #define ZYNQ_PIN_IS_MIO(type, pin) (pin >= ZYNQ##type##_PIN_MIO_MIN && \
108 pin <= ZYNQ##type##_PIN_MIO_MAX)
109 #define ZYNQ_PIN_IS_EMIO(type, pin) (pin >= ZYNQ##type##_PIN_EMIO_MIN && \
110 pin <= ZYNQ##type##_PIN_EMIO_MAX)
111
112 #define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
113 #define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
114 #define ZGPIO_LOCK_INIT(sc) \
115 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
116 "gpio", MTX_DEF)
117 #define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
118
119 enum zynq_gpio_type {
120 ZYNQ_7000 = 0,
121 ZYNQMP,
122 };
123
124 struct zynq_gpio_conf {
125 char *name;
126 enum zynq_gpio_type type;
127 uint32_t nbanks;
128 uint32_t maxpin;
129 uint32_t bank_min[ZYNQMP_MAX_BANK];
130 uint32_t bank_max[ZYNQMP_MAX_BANK];
131 };
132
133 struct zy7_gpio_softc {
134 device_t dev;
135 device_t busdev;
136 struct mtx sc_mtx;
137 struct resource *mem_res; /* Memory resource */
138 struct zynq_gpio_conf *conf;
139 };
140
141 static struct zynq_gpio_conf z7_gpio_conf = {
142 .name = "Zynq-7000 GPIO Controller",
143 .type = ZYNQ_7000,
144 .nbanks = ZYNQ7_MAX_BANK,
145 .maxpin = ZYNQ7_PIN_EMIO_MAX,
146 .bank_min[0] = ZYNQ_BANK_PIN_MIN(7, 0),
147 .bank_max[0] = ZYNQ_BANK_PIN_MAX(7, 0),
148 .bank_min[1] = ZYNQ_BANK_PIN_MIN(7, 1),
149 .bank_max[1] = ZYNQ_BANK_PIN_MAX(7, 1),
150 .bank_min[2] = ZYNQ_BANK_PIN_MIN(7, 2),
151 .bank_max[2] = ZYNQ_BANK_PIN_MAX(7, 2),
152 .bank_min[3] = ZYNQ_BANK_PIN_MIN(7, 3),
153 .bank_max[3] = ZYNQ_BANK_PIN_MAX(7, 3),
154 };
155
156 static struct zynq_gpio_conf zynqmp_gpio_conf = {
157 .name = "ZynqMP GPIO Controller",
158 .type = ZYNQMP,
159 .nbanks = ZYNQMP_MAX_BANK,
160 .maxpin = ZYNQMP_PIN_EMIO_MAX,
161 .bank_min[0] = ZYNQ_BANK_PIN_MIN(MP, 0),
162 .bank_max[0] = ZYNQ_BANK_PIN_MAX(MP, 0),
163 .bank_min[1] = ZYNQ_BANK_PIN_MIN(MP, 1),
164 .bank_max[1] = ZYNQ_BANK_PIN_MAX(MP, 1),
165 .bank_min[2] = ZYNQ_BANK_PIN_MIN(MP, 2),
166 .bank_max[2] = ZYNQ_BANK_PIN_MAX(MP, 2),
167 .bank_min[3] = ZYNQ_BANK_PIN_MIN(MP, 3),
168 .bank_max[3] = ZYNQ_BANK_PIN_MAX(MP, 3),
169 .bank_min[4] = ZYNQ_BANK_PIN_MIN(MP, 4),
170 .bank_max[4] = ZYNQ_BANK_PIN_MAX(MP, 4),
171 .bank_min[5] = ZYNQ_BANK_PIN_MIN(MP, 5),
172 .bank_max[5] = ZYNQ_BANK_PIN_MAX(MP, 5),
173 };
174
175 static struct ofw_compat_data compat_data[] = {
176 {"xlnx,zy7_gpio", (uintptr_t)&z7_gpio_conf},
177 {"xlnx,zynqmp-gpio-1.0", (uintptr_t)&zynqmp_gpio_conf},
178 {NULL, 0},
179 };
180
181 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val))
182 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off))
183
184 /* Xilinx Zynq-7000 GPIO register definitions:
185 */
186 #define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */
187 #define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */
188 #define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */
189 #define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */
190
191 #define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */
192 #define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */
193 #define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */
194 #define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */
195 #define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */
196 #define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */
197 #define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */
198 #define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */
199 #define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */
200
201 static device_t
zy7_gpio_get_bus(device_t dev)202 zy7_gpio_get_bus(device_t dev)
203 {
204 struct zy7_gpio_softc *sc;
205
206 sc = device_get_softc(dev);
207
208 return (sc->busdev);
209 }
210
211 static int
zy7_gpio_pin_max(device_t dev,int * maxpin)212 zy7_gpio_pin_max(device_t dev, int *maxpin)
213 {
214 struct zy7_gpio_softc *sc;
215
216 sc = device_get_softc(dev);
217 *maxpin = sc->conf->maxpin;
218 return (0);
219 }
220
221 static inline bool
zy7_pin_valid(device_t dev,uint32_t pin)222 zy7_pin_valid(device_t dev, uint32_t pin)
223 {
224 struct zy7_gpio_softc *sc;
225 int i;
226 bool found = false;
227
228 sc = device_get_softc(dev);
229 for (i = 0; i < sc->conf->nbanks; i++) {
230 if (pin >= sc->conf->bank_min[i] && pin <= sc->conf->bank_max[i]) {
231 found = true;
232 break;
233 }
234 }
235
236 return (found);
237 }
238
239 /* Get a specific pin's capabilities. */
240 static int
zy7_gpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)241 zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
242 {
243
244 if (!zy7_pin_valid(dev, pin))
245 return (EINVAL);
246
247 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
248
249 return (0);
250 }
251
252 /* Get a specific pin's name. */
253 static int
zy7_gpio_pin_getname(device_t dev,uint32_t pin,char * name)254 zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
255 {
256 struct zy7_gpio_softc *sc;
257 uint32_t emio_min;
258 bool is_mio;
259
260 sc = device_get_softc(dev);
261 if (!zy7_pin_valid(dev, pin))
262 return (EINVAL);
263
264 switch (sc->conf->type) {
265 case ZYNQ_7000:
266 is_mio = ZYNQ_PIN_IS_MIO(7, pin);
267 emio_min = ZYNQ7_PIN_EMIO_MIN;
268 break;
269 case ZYNQMP:
270 is_mio = ZYNQ_PIN_IS_MIO(MP, pin);
271 emio_min = ZYNQMP_PIN_EMIO_MIN;
272 break;
273 default:
274 return (EINVAL);
275 }
276 if (is_mio) {
277 snprintf(name, GPIOMAXNAME, "MIO_%d", pin);
278 name[GPIOMAXNAME - 1] = '\0';
279 } else {
280 snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - emio_min);
281 name[GPIOMAXNAME - 1] = '\0';
282 }
283
284 return (0);
285 }
286
287 /* Get a specific pin's current in/out/tri state. */
288 static int
zy7_gpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)289 zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
290 {
291 struct zy7_gpio_softc *sc = device_get_softc(dev);
292
293 if (!zy7_pin_valid(dev, pin))
294 return (EINVAL);
295
296 ZGPIO_LOCK(sc);
297
298 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
299 /* output */
300 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
301 *flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
302 else
303 *flags = GPIO_PIN_OUTPUT;
304 } else
305 /* input */
306 *flags = GPIO_PIN_INPUT;
307
308 ZGPIO_UNLOCK(sc);
309
310 return (0);
311 }
312
313 /* Set a specific pin's in/out/tri state. */
314 static int
zy7_gpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)315 zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
316 {
317 struct zy7_gpio_softc *sc = device_get_softc(dev);
318
319 if (!zy7_pin_valid(dev, pin))
320 return (EINVAL);
321
322 ZGPIO_LOCK(sc);
323
324 if ((flags & GPIO_PIN_OUTPUT) != 0) {
325 /* Output. Set or reset OEN too. */
326 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
327 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
328
329 if ((flags & GPIO_PIN_TRISTATE) != 0)
330 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
331 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
332 ~(1 << (pin & 31)));
333 else
334 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
335 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
336 (1 << (pin & 31)));
337 } else {
338 /* Input. Turn off OEN. */
339 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
340 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
341 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
342 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
343 }
344
345 ZGPIO_UNLOCK(sc);
346
347 return (0);
348 }
349
350 /* Set a specific output pin's value. */
351 static int
zy7_gpio_pin_set(device_t dev,uint32_t pin,unsigned int value)352 zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
353 {
354 struct zy7_gpio_softc *sc = device_get_softc(dev);
355
356 if (!zy7_pin_valid(dev, pin) || value > 1)
357 return (EINVAL);
358
359 /* Fancy register tricks allow atomic set or reset. */
360 if ((pin & 16) != 0)
361 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
362 (0xffff0000 ^ (0x10000 << (pin & 15))) |
363 (value << (pin & 15)));
364 else
365 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
366 (0xffff0000 ^ (0x10000 << (pin & 15))) |
367 (value << (pin & 15)));
368
369 return (0);
370 }
371
372 /* Get a specific pin's input value. */
373 static int
zy7_gpio_pin_get(device_t dev,uint32_t pin,unsigned int * value)374 zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
375 {
376 struct zy7_gpio_softc *sc = device_get_softc(dev);
377
378 if (!zy7_pin_valid(dev, pin))
379 return (EINVAL);
380
381 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
382
383 return (0);
384 }
385
386 /* Toggle a pin's output value. */
387 static int
zy7_gpio_pin_toggle(device_t dev,uint32_t pin)388 zy7_gpio_pin_toggle(device_t dev, uint32_t pin)
389 {
390 struct zy7_gpio_softc *sc = device_get_softc(dev);
391
392 if (!zy7_pin_valid(dev, pin))
393 return (EINVAL);
394
395 ZGPIO_LOCK(sc);
396
397 WR4(sc, ZY7_GPIO_DATA(pin >> 5),
398 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31)));
399
400 ZGPIO_UNLOCK(sc);
401
402 return (0);
403 }
404
405 static int
zy7_gpio_probe(device_t dev)406 zy7_gpio_probe(device_t dev)
407 {
408 struct zynq_gpio_conf *conf;
409
410 if (!ofw_bus_status_okay(dev))
411 return (ENXIO);
412
413 conf = (struct zynq_gpio_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
414 if (conf == 0)
415 return (ENXIO);
416
417 device_set_desc(dev, conf->name);
418 return (0);
419 }
420
421 static int zy7_gpio_detach(device_t dev);
422
423 static int
zy7_gpio_attach(device_t dev)424 zy7_gpio_attach(device_t dev)
425 {
426 struct zy7_gpio_softc *sc = device_get_softc(dev);
427 int rid;
428
429 sc->dev = dev;
430 sc->conf = (struct zynq_gpio_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
431
432 ZGPIO_LOCK_INIT(sc);
433
434 /* Allocate memory. */
435 rid = 0;
436 sc->mem_res = bus_alloc_resource_any(dev,
437 SYS_RES_MEMORY, &rid, RF_ACTIVE);
438 if (sc->mem_res == NULL) {
439 device_printf(dev, "Can't allocate memory for device");
440 zy7_gpio_detach(dev);
441 return (ENOMEM);
442 }
443
444 sc->busdev = gpiobus_attach_bus(dev);
445 if (sc->busdev == NULL) {
446 zy7_gpio_detach(dev);
447 return (ENOMEM);
448 }
449
450 return (0);
451 }
452
453 static int
zy7_gpio_detach(device_t dev)454 zy7_gpio_detach(device_t dev)
455 {
456 struct zy7_gpio_softc *sc = device_get_softc(dev);
457
458 gpiobus_detach_bus(dev);
459
460 if (sc->mem_res != NULL) {
461 /* Release memory resource. */
462 bus_release_resource(dev, SYS_RES_MEMORY,
463 rman_get_rid(sc->mem_res), sc->mem_res);
464 }
465
466 ZGPIO_LOCK_DESTROY(sc);
467
468 return (0);
469 }
470
471 static device_method_t zy7_gpio_methods[] = {
472 /* device_if */
473 DEVMETHOD(device_probe, zy7_gpio_probe),
474 DEVMETHOD(device_attach, zy7_gpio_attach),
475 DEVMETHOD(device_detach, zy7_gpio_detach),
476
477 /* GPIO protocol */
478 DEVMETHOD(gpio_get_bus, zy7_gpio_get_bus),
479 DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max),
480 DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname),
481 DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags),
482 DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps),
483 DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags),
484 DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get),
485 DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set),
486 DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle),
487
488 DEVMETHOD_END
489 };
490
491 static driver_t zy7_gpio_driver = {
492 "gpio",
493 zy7_gpio_methods,
494 sizeof(struct zy7_gpio_softc),
495 };
496
497 EARLY_DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, 0, 0,
498 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
499