Searched refs:ZEROReg (Results 1 – 3 of 3) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips32r6InstrInfo.td | 1041 multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> { 1043 (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 1045 (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 1047 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 1059 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
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H A D | MipsInstrInfo.td | 3118 multiclass MaterializeImms<ValueType VT, Register ZEROReg, 3135 def : MipsPat<(VT ORiPred:$imm), (ORiOp ZEROReg, imm:$imm)>; 3136 def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>; 3257 Register ZEROReg> { 3259 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 3261 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 3282 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 3295 Instruction SLTuOp, Register ZEROReg> { 3299 (SLTuOp ZEROReg, RC:$lhs)>; 3303 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
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H A D | MipsSEInstrInfo.cpp | 596 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in loadImmediate() local 615 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) in loadImmediate()
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