1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015,2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifdef __arm__ 31 #include <arm/armreg.h> 32 #else /* !__arm__ */ 33 34 #ifndef _MACHINE_ARMREG_H_ 35 #define _MACHINE_ARMREG_H_ 36 37 #define INSN_SIZE 4 38 39 #define MRS_MASK 0xfff00000 40 #define MRS_VALUE 0xd5300000 41 #define MRS_SPECIAL(insn) ((insn) & 0x000fffe0) 42 #define MRS_REGISTER(insn) ((insn) & 0x0000001f) 43 #define MRS_Op0_SHIFT 19 44 #define MRS_Op0_MASK 0x00080000 45 #define MRS_Op1_SHIFT 16 46 #define MRS_Op1_MASK 0x00070000 47 #define MRS_CRn_SHIFT 12 48 #define MRS_CRn_MASK 0x0000f000 49 #define MRS_CRm_SHIFT 8 50 #define MRS_CRm_MASK 0x00000f00 51 #define MRS_Op2_SHIFT 5 52 #define MRS_Op2_MASK 0x000000e0 53 #define MRS_Rt_SHIFT 0 54 #define MRS_Rt_MASK 0x0000001f 55 #define __MRS_REG(op0, op1, crn, crm, op2) \ 56 (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \ 57 ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) | \ 58 ((op2) << MRS_Op2_SHIFT)) 59 #define MRS_REG(reg) \ 60 __MRS_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) 61 62 #define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ 63 S##op0##_##op1##_C##crn##_C##crm##_##op2 64 #define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ 65 __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) 66 #define MRS_REG_ALT_NAME(reg) \ 67 _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) 68 69 70 #define READ_SPECIALREG(reg) \ 71 ({ uint64_t _val; \ 72 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ 73 _val; \ 74 }) 75 #define WRITE_SPECIALREG(reg, _val) \ 76 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) 77 78 #define UL(x) UINT64_C(x) 79 80 /* AFSR0_EL1 - Auxiliary Fault Status Register 0 */ 81 #define AFSR0_EL1_REG MRS_REG_ALT_NAME(AFSR0_EL1) 82 #define AFSR0_EL1_op0 3 83 #define AFSR0_EL1_op1 0 84 #define AFSR0_EL1_CRn 5 85 #define AFSR0_EL1_CRm 1 86 #define AFSR0_EL1_op2 0 87 88 /* AFSR0_EL12 */ 89 #define AFSR0_EL12_REG MRS_REG_ALT_NAME(AFSR0_EL12) 90 #define AFSR0_EL12_op0 3 91 #define AFSR0_EL12_op1 5 92 #define AFSR0_EL12_CRn 5 93 #define AFSR0_EL12_CRm 1 94 #define AFSR0_EL12_op2 0 95 96 /* AFSR1_EL1 - Auxiliary Fault Status Register 1 */ 97 #define AFSR1_EL1_REG MRS_REG_ALT_NAME(AFSR1_EL1) 98 #define AFSR1_EL1_op0 3 99 #define AFSR1_EL1_op1 0 100 #define AFSR1_EL1_CRn 5 101 #define AFSR1_EL1_CRm 1 102 #define AFSR1_EL1_op2 1 103 104 /* AFSR1_EL12 */ 105 #define AFSR1_EL12_REG MRS_REG_ALT_NAME(AFSR1_EL12) 106 #define AFSR1_EL12_op0 3 107 #define AFSR1_EL12_op1 5 108 #define AFSR1_EL12_CRn 5 109 #define AFSR1_EL12_CRm 1 110 #define AFSR1_EL12_op2 1 111 112 /* AMAIR_EL1 - Auxiliary Memory Attribute Indirection Register */ 113 #define AMAIR_EL1_REG MRS_REG_ALT_NAME(AMAIR_EL1) 114 #define AMAIR_EL1_op0 3 115 #define AMAIR_EL1_op1 0 116 #define AMAIR_EL1_CRn 10 117 #define AMAIR_EL1_CRm 3 118 #define AMAIR_EL1_op2 0 119 120 /* AMAIR_EL12 */ 121 #define AMAIR_EL12_REG MRS_REG_ALT_NAME(AMAIR_EL12) 122 #define AMAIR_EL12_op0 3 123 #define AMAIR_EL12_op1 5 124 #define AMAIR_EL12_CRn 10 125 #define AMAIR_EL12_CRm 3 126 #define AMAIR_EL12_op2 0 127 128 /* APDAKeyHi_EL1 */ 129 #define APDAKeyHi_EL1_REG MRS_REG_ALT_NAME(APDAKeyHi_EL1) 130 #define APDAKeyHi_EL1_op0 3 131 #define APDAKeyHi_EL1_op1 0 132 #define APDAKeyHi_EL1_CRn 2 133 #define APDAKeyHi_EL1_CRm 2 134 #define APDAKeyHi_EL1_op2 1 135 136 /* APDAKeyLo_EL1 */ 137 #define APDAKeyLo_EL1_REG MRS_REG_ALT_NAME(APDAKeyLo_EL1) 138 #define APDAKeyLo_EL1_op0 3 139 #define APDAKeyLo_EL1_op1 0 140 #define APDAKeyLo_EL1_CRn 2 141 #define APDAKeyLo_EL1_CRm 2 142 #define APDAKeyLo_EL1_op2 0 143 144 /* APDBKeyHi_EL1 */ 145 #define APDBKeyHi_EL1_REG MRS_REG_ALT_NAME(APDBKeyHi_EL1) 146 #define APDBKeyHi_EL1_op0 3 147 #define APDBKeyHi_EL1_op1 0 148 #define APDBKeyHi_EL1_CRn 2 149 #define APDBKeyHi_EL1_CRm 2 150 #define APDBKeyHi_EL1_op2 3 151 152 /* APDBKeyLo_EL1 */ 153 #define APDBKeyLo_EL1_REG MRS_REG_ALT_NAME(APDBKeyLo_EL1) 154 #define APDBKeyLo_EL1_op0 3 155 #define APDBKeyLo_EL1_op1 0 156 #define APDBKeyLo_EL1_CRn 2 157 #define APDBKeyLo_EL1_CRm 2 158 #define APDBKeyLo_EL1_op2 2 159 160 /* APGAKeyHi_EL1 */ 161 #define APGAKeyHi_EL1_REG MRS_REG_ALT_NAME(APGAKeyHi_EL1) 162 #define APGAKeyHi_EL1_op0 3 163 #define APGAKeyHi_EL1_op1 0 164 #define APGAKeyHi_EL1_CRn 2 165 #define APGAKeyHi_EL1_CRm 3 166 #define APGAKeyHi_EL1_op2 1 167 168 /* APGAKeyLo_EL1 */ 169 #define APGAKeyLo_EL1_REG MRS_REG_ALT_NAME(APGAKeyLo_EL1) 170 #define APGAKeyLo_EL1_op0 3 171 #define APGAKeyLo_EL1_op1 0 172 #define APGAKeyLo_EL1_CRn 2 173 #define APGAKeyLo_EL1_CRm 3 174 #define APGAKeyLo_EL1_op2 0 175 176 /* APIAKeyHi_EL1 */ 177 #define APIAKeyHi_EL1_REG MRS_REG_ALT_NAME(APIAKeyHi_EL1) 178 #define APIAKeyHi_EL1_op0 3 179 #define APIAKeyHi_EL1_op1 0 180 #define APIAKeyHi_EL1_CRn 2 181 #define APIAKeyHi_EL1_CRm 1 182 #define APIAKeyHi_EL1_op2 1 183 184 /* APIAKeyLo_EL1 */ 185 #define APIAKeyLo_EL1_REG MRS_REG_ALT_NAME(APIAKeyLo_EL1) 186 #define APIAKeyLo_EL1_op0 3 187 #define APIAKeyLo_EL1_op1 0 188 #define APIAKeyLo_EL1_CRn 2 189 #define APIAKeyLo_EL1_CRm 1 190 #define APIAKeyLo_EL1_op2 0 191 192 /* APIBKeyHi_EL1 */ 193 #define APIBKeyHi_EL1_REG MRS_REG_ALT_NAME(APIBKeyHi_EL1) 194 #define APIBKeyHi_EL1_op0 3 195 #define APIBKeyHi_EL1_op1 0 196 #define APIBKeyHi_EL1_CRn 2 197 #define APIBKeyHi_EL1_CRm 1 198 #define APIBKeyHi_EL1_op2 3 199 200 /* APIBKeyLo_EL1 */ 201 #define APIBKeyLo_EL1_REG MRS_REG_ALT_NAME(APIBKeyLo_EL1) 202 #define APIBKeyLo_EL1_op0 3 203 #define APIBKeyLo_EL1_op1 0 204 #define APIBKeyLo_EL1_CRn 2 205 #define APIBKeyLo_EL1_CRm 1 206 #define APIBKeyLo_EL1_op2 2 207 208 /* CCSIDR_EL1 - Cache Size ID Register */ 209 #define CCSIDR_NumSets_MASK 0x0FFFE000 210 #define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000 211 #define CCSIDR_NumSets_SHIFT 13 212 #define CCSIDR_NumSets64_SHIFT 32 213 #define CCSIDR_Assoc_MASK 0x00001FF8 214 #define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8 215 #define CCSIDR_Assoc_SHIFT 3 216 #define CCSIDR_Assoc64_SHIFT 3 217 #define CCSIDR_LineSize_MASK 0x7 218 #define CCSIDR_NSETS(idr) \ 219 (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT) 220 #define CCSIDR_ASSOC(idr) \ 221 (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) 222 #define CCSIDR_NSETS_64(idr) \ 223 (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT) 224 #define CCSIDR_ASSOC_64(idr) \ 225 (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT) 226 227 /* CLIDR_EL1 - Cache level ID register */ 228 #define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */ 229 #define CLIDR_CTYPE_IO 0x1 /* Instruction only */ 230 #define CLIDR_CTYPE_DO 0x2 /* Data only */ 231 #define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */ 232 #define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */ 233 234 /* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ 235 #define CNTKCTL_EL1 MRS_REG(CNTKCTL_EL0) 236 #define CNTKCTL_EL1_op0 3 237 #define CNTKCTL_EL1_op1 0 238 #define CNTKCTL_EL1_CRn 14 239 #define CNTKCTL_EL1_CRm 1 240 #define CNTKCTL_EL1_op2 0 241 242 /* CNTKCTL_EL12 - Counter-timer Kernel Control Register */ 243 #define CNTKCTL_EL12 MRS_REG(CNTKCTL_EL0) 244 #define CNTKCTL_EL12_op0 3 245 #define CNTKCTL_EL12_op1 5 246 #define CNTKCTL_EL12_CRn 14 247 #define CNTKCTL_EL12_CRm 1 248 #define CNTKCTL_EL12_op2 0 249 250 /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */ 251 #define CNTP_CTL_EL0 MRS_REG(CNTP_CTL_EL0) 252 #define CNTP_CTL_EL0_op0 3 253 #define CNTP_CTL_EL0_op1 3 254 #define CNTP_CTL_EL0_CRn 14 255 #define CNTP_CTL_EL0_CRm 2 256 #define CNTP_CTL_EL0_op2 1 257 #define CNTP_CTL_ENABLE (1 << 0) 258 #define CNTP_CTL_IMASK (1 << 1) 259 #define CNTP_CTL_ISTATUS (1 << 2) 260 261 /* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */ 262 #define CNTP_CVAL_EL0 MRS_REG(CNTP_CVAL_EL0) 263 #define CNTP_CVAL_EL0_op0 3 264 #define CNTP_CVAL_EL0_op1 3 265 #define CNTP_CVAL_EL0_CRn 14 266 #define CNTP_CVAL_EL0_CRm 2 267 #define CNTP_CVAL_EL0_op2 2 268 269 /* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */ 270 #define CNTP_TVAL_EL0 MRS_REG(CNTP_TVAL_EL0) 271 #define CNTP_TVAL_EL0_op0 3 272 #define CNTP_TVAL_EL0_op1 3 273 #define CNTP_TVAL_EL0_CRn 14 274 #define CNTP_TVAL_EL0_CRm 2 275 #define CNTP_TVAL_EL0_op2 0 276 277 /* CNTPCT_EL0 - Counter-timer Physical Count register */ 278 #define CNTPCT_EL0 MRS_REG(CNTPCT_EL0) 279 #define CNTPCT_EL0_op0 3 280 #define CNTPCT_EL0_op1 3 281 #define CNTPCT_EL0_CRn 14 282 #define CNTPCT_EL0_CRm 0 283 #define CNTPCT_EL0_op2 1 284 285 /* CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register */ 286 #define CNTV_CTL_EL0 MRS_REG(CNTV_CTL_EL0) 287 #define CNTV_CTL_EL0_op0 3 288 #define CNTV_CTL_EL0_op1 3 289 #define CNTV_CTL_EL0_CRn 14 290 #define CNTV_CTL_EL0_CRm 3 291 #define CNTV_CTL_EL0_op2 1 292 293 /* CNTV_CTL_EL02 - Counter-timer Virtual Timer Control register */ 294 #define CNTV_CTL_EL02 MRS_REG(CNTV_CTL_EL02) 295 #define CNTV_CTL_EL02_op0 3 296 #define CNTV_CTL_EL02_op1 5 297 #define CNTV_CTL_EL02_CRn 14 298 #define CNTV_CTL_EL02_CRm 3 299 #define CNTV_CTL_EL02_op2 1 300 301 /* CNTV_CVAL_EL0 - Counter-timer Virtual Timer CompareValue register */ 302 #define CNTV_CVAL_EL0 MRS_REG(CNTV_CVAL_EL0) 303 #define CNTV_CVAL_EL0_op0 3 304 #define CNTV_CVAL_EL0_op1 3 305 #define CNTV_CVAL_EL0_CRn 14 306 #define CNTV_CVAL_EL0_CRm 3 307 #define CNTV_CVAL_EL0_op2 2 308 309 /* CNTV_CVAL_EL02 - Counter-timer Virtual Timer CompareValue register */ 310 #define CNTV_CVAL_EL02 MRS_REG(CNTV_CVAL_EL02) 311 #define CNTV_CVAL_EL02_op0 3 312 #define CNTV_CVAL_EL02_op1 5 313 #define CNTV_CVAL_EL02_CRn 14 314 #define CNTV_CVAL_EL02_CRm 3 315 #define CNTV_CVAL_EL02_op2 2 316 317 /* CONTEXTIDR_EL1 - Context ID register */ 318 #define CONTEXTIDR_EL1 MRS_REG(CONTEXTIDR_EL1) 319 #define CONTEXTIDR_EL1_REG MRS_REG_ALT_NAME(CONTEXTIDR_EL1) 320 #define CONTEXTIDR_EL1_op0 3 321 #define CONTEXTIDR_EL1_op1 0 322 #define CONTEXTIDR_EL1_CRn 13 323 #define CONTEXTIDR_EL1_CRm 0 324 #define CONTEXTIDR_EL1_op2 1 325 326 /* CONTEXTIDR_EL12 */ 327 #define CONTEXTIDR_EL12_REG MRS_REG_ALT_NAME(CONTEXTIDR_EL12) 328 #define CONTEXTIDR_EL12_op0 3 329 #define CONTEXTIDR_EL12_op1 5 330 #define CONTEXTIDR_EL12_CRn 13 331 #define CONTEXTIDR_EL12_CRm 0 332 #define CONTEXTIDR_EL12_op2 1 333 334 /* CPACR_EL1 */ 335 #define CPACR_EL1_REG MRS_REG_ALT_NAME(CPACR_EL1) 336 #define CPACR_EL1_op0 3 337 #define CPACR_EL1_op1 0 338 #define CPACR_EL1_CRn 1 339 #define CPACR_EL1_CRm 0 340 #define CPACR_EL1_op2 2 341 #define CPACR_ZEN_MASK (0x3 << 16) 342 #define CPACR_ZEN_TRAP_ALL1 (0x0 << 16) /* Traps from EL0 and EL1 */ 343 #define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */ 344 #define CPACR_ZEN_TRAP_ALL2 (0x2 << 16) /* Traps from EL0 and EL1 */ 345 #define CPACR_ZEN_TRAP_NONE (0x3 << 16) /* No traps */ 346 #define CPACR_FPEN_MASK (0x3 << 20) 347 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 348 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 349 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 350 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 351 #define CPACR_TTA (0x1 << 28) 352 353 /* CPACR_EL12 */ 354 #define CPACR_EL12_REG MRS_REG_ALT_NAME(CPACR_EL12) 355 #define CPACR_EL12_op0 3 356 #define CPACR_EL12_op1 5 357 #define CPACR_EL12_CRn 1 358 #define CPACR_EL12_CRm 0 359 #define CPACR_EL12_op2 2 360 361 /* CSSELR_EL1 - Cache size selection register */ 362 #define CSSELR_Level(i) (i << 1) 363 #define CSSELR_InD 0x00000001 364 365 /* CTR_EL0 - Cache Type Register */ 366 #define CTR_EL0 MRS_REG(CTR_EL0) 367 #define CTR_EL0_REG MRS_REG_ALT_NAME(CTR_EL0) 368 #define CTR_EL0_op0 3 369 #define CTR_EL0_op1 3 370 #define CTR_EL0_CRn 0 371 #define CTR_EL0_CRm 0 372 #define CTR_EL0_op2 1 373 #define CTR_RES1 (1 << 31) 374 #define CTR_TminLine_SHIFT 32 375 #define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT) 376 #define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK) 377 #define CTR_DIC_SHIFT 29 378 #define CTR_DIC_WIDTH 1 379 #define CTR_DIC_MASK (0x1 << CTR_DIC_SHIFT) 380 #define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK) 381 #define CTR_DIC_NONE (0x0 << CTR_DIC_SHIFT) 382 #define CTR_DIC_IMPL (0x1 << CTR_DIC_SHIFT) 383 #define CTR_IDC_SHIFT 28 384 #define CTR_IDC_WIDTH 1 385 #define CTR_IDC_MASK (0x1 << CTR_IDC_SHIFT) 386 #define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK) 387 #define CTR_IDC_NONE (0x0 << CTR_IDC_SHIFT) 388 #define CTR_IDC_IMPL (0x1 << CTR_IDC_SHIFT) 389 #define CTR_CWG_SHIFT 24 390 #define CTR_CWG_WIDTH 4 391 #define CTR_CWG_MASK (0xf << CTR_CWG_SHIFT) 392 #define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK) 393 #define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT)) 394 #define CTR_ERG_SHIFT 20 395 #define CTR_ERG_WIDTH 4 396 #define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) 397 #define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) 398 #define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) 399 #define CTR_DLINE_SHIFT 16 400 #define CTR_DLINE_WIDTH 4 401 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 402 #define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) 403 #define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) 404 #define CTR_L1IP_SHIFT 14 405 #define CTR_L1IP_WIDTH 2 406 #define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) 407 #define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) 408 #define CTR_L1IP_VIPT (2 << CTR_L1IP_SHIFT) 409 #define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) 410 #define CTR_ILINE_SHIFT 0 411 #define CTR_ILINE_WIDTH 4 412 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 413 #define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) 414 #define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) 415 416 /* CurrentEL - Current Exception Level */ 417 #define CURRENTEL_EL_SHIFT 2 418 #define CURRENTEL_EL_MASK (0x3 << CURRENTEL_EL_SHIFT) 419 #define CURRENTEL_EL_EL0 (0x0 << CURRENTEL_EL_SHIFT) 420 #define CURRENTEL_EL_EL1 (0x1 << CURRENTEL_EL_SHIFT) 421 #define CURRENTEL_EL_EL2 (0x2 << CURRENTEL_EL_SHIFT) 422 #define CURRENTEL_EL_EL3 (0x3 << CURRENTEL_EL_SHIFT) 423 424 /* DAIFSet/DAIFClear */ 425 #define DAIF_D (1 << 3) 426 #define DAIF_A (1 << 2) 427 #define DAIF_I (1 << 1) 428 #define DAIF_F (1 << 0) 429 #define DAIF_ALL (DAIF_D | DAIF_A | DAIF_I | DAIF_F) 430 #define DAIF_INTR (DAIF_I | DAIF_F) /* All exceptions that pass */ 431 /* through the intr framework */ 432 433 /* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */ 434 #define DBGBCR_EL1_op0 2 435 #define DBGBCR_EL1_op1 0 436 #define DBGBCR_EL1_CRn 0 437 /* DBGBCR_EL1_CRm indicates which watchpoint this register is for */ 438 #define DBGBCR_EL1_op2 5 439 #define DBGBCR_EN 0x1 440 #define DBGBCR_PMC_SHIFT 1 441 #define DBGBCR_PMC (0x3 << DBGBCR_PMC_SHIFT) 442 #define DBGBCR_PMC_EL1 (0x1 << DBGBCR_PMC_SHIFT) 443 #define DBGBCR_PMC_EL0 (0x2 << DBGBCR_PMC_SHIFT) 444 #define DBGBCR_BAS_SHIFT 5 445 #define DBGBCR_BAS (0xf << DBGBCR_BAS_SHIFT) 446 #define DBGBCR_HMC_SHIFT 13 447 #define DBGBCR_HMC (0x1 << DBGBCR_HMC_SHIFT) 448 #define DBGBCR_SSC_SHIFT 14 449 #define DBGBCR_SSC (0x3 << DBGBCR_SSC_SHIFT) 450 #define DBGBCR_LBN_SHIFT 16 451 #define DBGBCR_LBN (0xf << DBGBCR_LBN_SHIFT) 452 #define DBGBCR_BT_SHIFT 20 453 #define DBGBCR_BT (0xf << DBGBCR_BT_SHIFT) 454 455 /* DBGBVR<n>_EL1 - Debug Breakpoint Value Registers */ 456 #define DBGBVR_EL1_op0 2 457 #define DBGBVR_EL1_op1 0 458 #define DBGBVR_EL1_CRn 0 459 /* DBGBVR_EL1_CRm indicates which watchpoint this register is for */ 460 #define DBGBVR_EL1_op2 4 461 462 /* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */ 463 #define DBGWCR_EL1_op0 2 464 #define DBGWCR_EL1_op1 0 465 #define DBGWCR_EL1_CRn 0 466 /* DBGWCR_EL1_CRm indicates which watchpoint this register is for */ 467 #define DBGWCR_EL1_op2 7 468 #define DBGWCR_EN 0x1 469 #define DBGWCR_PAC_SHIFT 1 470 #define DBGWCR_PAC (0x3 << DBGWCR_PAC_SHIFT) 471 #define DBGWCR_PAC_EL1 (0x1 << DBGWCR_PAC_SHIFT) 472 #define DBGWCR_PAC_EL0 (0x2 << DBGWCR_PAC_SHIFT) 473 #define DBGWCR_LSC_SHIFT 3 474 #define DBGWCR_LSC (0x3 << DBGWCR_LSC_SHIFT) 475 #define DBGWCR_BAS_SHIFT 5 476 #define DBGWCR_BAS (0xff << DBGWCR_BAS_SHIFT) 477 #define DBGWCR_HMC_SHIFT 13 478 #define DBGWCR_HMC (0x1 << DBGWCR_HMC_SHIFT) 479 #define DBGWCR_SSC_SHIFT 14 480 #define DBGWCR_SSC (0x3 << DBGWCR_SSC_SHIFT) 481 #define DBGWCR_LBN_SHIFT 16 482 #define DBGWCR_LBN (0xf << DBGWCR_LBN_SHIFT) 483 #define DBGWCR_WT_SHIFT 20 484 #define DBGWCR_WT (0x1 << DBGWCR_WT_SHIFT) 485 #define DBGWCR_MASK_SHIFT 24 486 #define DBGWCR_MASK (0x1f << DBGWCR_MASK_SHIFT) 487 488 /* DBGWVR<n>_EL1 - Debug Watchpoint Value Registers */ 489 #define DBGWVR_EL1_op0 2 490 #define DBGWVR_EL1_op1 0 491 #define DBGWVR_EL1_CRn 0 492 /* DBGWVR_EL1_CRm indicates which watchpoint this register is for */ 493 #define DBGWVR_EL1_op2 6 494 495 /* DCZID_EL0 - Data Cache Zero ID register */ 496 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 497 #define DCZID_BS_SHIFT 0 498 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 499 #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 500 501 /* DBGAUTHSTATUS_EL1 */ 502 #define DBGAUTHSTATUS_EL1 MRS_REG(DBGAUTHSTATUS_EL1) 503 #define DBGAUTHSTATUS_EL1_op0 2 504 #define DBGAUTHSTATUS_EL1_op1 0 505 #define DBGAUTHSTATUS_EL1_CRn 7 506 #define DBGAUTHSTATUS_EL1_CRm 14 507 #define DBGAUTHSTATUS_EL1_op2 6 508 509 /* DBGCLAIMCLR_EL1 */ 510 #define DBGCLAIMCLR_EL1 MRS_REG(DBGCLAIMCLR_EL1) 511 #define DBGCLAIMCLR_EL1_op0 2 512 #define DBGCLAIMCLR_EL1_op1 0 513 #define DBGCLAIMCLR_EL1_CRn 7 514 #define DBGCLAIMCLR_EL1_CRm 9 515 #define DBGCLAIMCLR_EL1_op2 6 516 517 /* DBGCLAIMSET_EL1 */ 518 #define DBGCLAIMSET_EL1 MRS_REG(DBGCLAIMSET_EL1) 519 #define DBGCLAIMSET_EL1_op0 2 520 #define DBGCLAIMSET_EL1_op1 0 521 #define DBGCLAIMSET_EL1_CRn 7 522 #define DBGCLAIMSET_EL1_CRm 8 523 #define DBGCLAIMSET_EL1_op2 6 524 525 /* DBGPRCR_EL1 */ 526 #define DBGPRCR_EL1 MRS_REG(DBGPRCR_EL1) 527 #define DBGPRCR_EL1_op0 2 528 #define DBGPRCR_EL1_op1 0 529 #define DBGPRCR_EL1_CRn 1 530 #define DBGPRCR_EL1_CRm 4 531 #define DBGPRCR_EL1_op2 4 532 533 /* ELR_EL1 */ 534 #define ELR_EL1_REG MRS_REG_ALT_NAME(ELR_EL1) 535 #define ELR_EL1_op0 3 536 #define ELR_EL1_op1 0 537 #define ELR_EL1_CRn 4 538 #define ELR_EL1_CRm 0 539 #define ELR_EL1_op2 1 540 541 /* ELR_EL12 */ 542 #define ELR_EL12_REG MRS_REG_ALT_NAME(ELR_EL12) 543 #define ELR_EL12_op0 3 544 #define ELR_EL12_op1 5 545 #define ELR_EL12_CRn 4 546 #define ELR_EL12_CRm 0 547 #define ELR_EL12_op2 1 548 549 /* ESR_ELx */ 550 #define ESR_ELx_ISS_MASK 0x01ffffff 551 #define ISS_FP_TFV_SHIFT 23 552 #define ISS_FP_TFV (0x01 << ISS_FP_TFV_SHIFT) 553 #define ISS_FP_IOF 0x01 554 #define ISS_FP_DZF 0x02 555 #define ISS_FP_OFF 0x04 556 #define ISS_FP_UFF 0x08 557 #define ISS_FP_IXF 0x10 558 #define ISS_FP_IDF 0x80 559 #define ISS_INSN_FnV (0x01 << 10) 560 #define ISS_INSN_EA (0x01 << 9) 561 #define ISS_INSN_S1PTW (0x01 << 7) 562 #define ISS_INSN_IFSC_MASK (0x1f << 0) 563 564 #define ISS_WFx_TI_SHIFT 0 565 #define ISS_WFx_TI_MASK (0x03 << ISS_WFx_TI_SHIFT) 566 #define ISS_WFx_TI_WFI (0x00 << ISS_WFx_TI_SHIFT) 567 #define ISS_WFx_TI_WFE (0x01 << ISS_WFx_TI_SHIFT) 568 #define ISS_WFx_TI_WFIT (0x02 << ISS_WFx_TI_SHIFT) 569 #define ISS_WFx_TI_WFET (0x03 << ISS_WFx_TI_SHIFT) 570 #define ISS_WFx_RV_SHIFT 2 571 #define ISS_WFx_RV_MASK (0x01 << ISS_WFx_RV_SHIFT) 572 #define ISS_WFx_RV_INVALID (0x00 << ISS_WFx_RV_SHIFT) 573 #define ISS_WFx_RV_VALID (0x01 << ISS_WFx_RV_SHIFT) 574 #define ISS_WFx_RN_SHIFT 5 575 #define ISS_WFx_RN_MASK (0x1f << ISS_WFx_RN_SHIFT) 576 #define ISS_WFx_RN(x) (((x) & ISS_WFx_RN_MASK) >> ISS_WFx_RN_SHIFT) 577 #define ISS_WFx_COND_SHIFT 20 578 #define ISS_WFx_COND_MASK (0x0f << ISS_WFx_COND_SHIFT) 579 #define ISS_WFx_CV_SHIFT 24 580 #define ISS_WFx_CV_MASK (0x01 << ISS_WFx_CV_SHIFT) 581 #define ISS_WFx_CV_INVALID (0x00 << ISS_WFx_CV_SHIFT) 582 #define ISS_WFx_CV_VALID (0x01 << ISS_WFx_CV_SHIFT) 583 584 #define ISS_MSR_DIR_SHIFT 0 585 #define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT) 586 #define ISS_MSR_Rt_SHIFT 5 587 #define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT) 588 #define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) 589 #define ISS_MSR_CRm_SHIFT 1 590 #define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT) 591 #define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) 592 #define ISS_MSR_CRn_SHIFT 10 593 #define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT) 594 #define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) 595 #define ISS_MSR_OP1_SHIFT 14 596 #define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT) 597 #define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) 598 #define ISS_MSR_OP2_SHIFT 17 599 #define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT) 600 #define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) 601 #define ISS_MSR_OP0_SHIFT 20 602 #define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT) 603 #define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) 604 #define ISS_MSR_REG_MASK \ 605 (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | \ 606 ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK) 607 #define ISS_MSR_REG(reg) \ 608 (((reg ## _op0) << ISS_MSR_OP0_SHIFT) | \ 609 ((reg ## _op1) << ISS_MSR_OP1_SHIFT) | \ 610 ((reg ## _CRn) << ISS_MSR_CRn_SHIFT) | \ 611 ((reg ## _CRm) << ISS_MSR_CRm_SHIFT) | \ 612 ((reg ## _op2) << ISS_MSR_OP2_SHIFT)) 613 614 #define ISS_DATA_ISV_SHIFT 24 615 #define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT) 616 #define ISS_DATA_SAS_SHIFT 22 617 #define ISS_DATA_SAS_MASK (0x03 << ISS_DATA_SAS_SHIFT) 618 #define ISS_DATA_SSE_SHIFT 21 619 #define ISS_DATA_SSE (0x01 << ISS_DATA_SSE_SHIFT) 620 #define ISS_DATA_SRT_SHIFT 16 621 #define ISS_DATA_SRT_MASK (0x1f << ISS_DATA_SRT_SHIFT) 622 #define ISS_DATA_SF (0x01 << 15) 623 #define ISS_DATA_AR (0x01 << 14) 624 #define ISS_DATA_FnV (0x01 << 10) 625 #define ISS_DATA_EA (0x01 << 9) 626 #define ISS_DATA_CM (0x01 << 8) 627 #define ISS_DATA_S1PTW (0x01 << 7) 628 #define ISS_DATA_WnR_SHIFT 6 629 #define ISS_DATA_WnR (0x01 << ISS_DATA_WnR_SHIFT) 630 #define ISS_DATA_DFSC_MASK (0x3f << 0) 631 #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 632 #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 633 #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 634 #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 635 #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 636 #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 637 #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 638 #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 639 #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 640 #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 641 #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 642 #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 643 #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 644 #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 645 #define ISS_DATA_DFSC_EXT (0x10 << 0) 646 #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 647 #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 648 #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 649 #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 650 #define ISS_DATA_DFSC_ECC (0x18 << 0) 651 #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 652 #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 653 #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 654 #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 655 #define ISS_DATA_DFSC_ALIGN (0x21 << 0) 656 #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 657 #define ESR_ELx_IL (0x01 << 25) 658 #define ESR_ELx_EC_SHIFT 26 659 #define ESR_ELx_EC_MASK (0x3f << 26) 660 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 661 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 662 #define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ 663 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 664 #define EXCP_BTI 0x0d /* Branch Target Exception */ 665 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 666 #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ 667 #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ 668 #define EXCP_HVC 0x16 /* HVC trap */ 669 #define EXCP_MSR 0x18 /* MSR/MRS trap */ 670 #define EXCP_SVE 0x19 /* SVE trap */ 671 #define EXCP_FPAC 0x1c /* Faulting PAC trap */ 672 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 673 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 674 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 675 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 676 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 677 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 678 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 679 #define EXCP_SERROR 0x2f /* SError interrupt */ 680 #define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ 681 #define EXCP_BRKPT_EL1 0x31 /* Hardware breakpoint, from same EL */ 682 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 683 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 684 #define EXCP_WATCHPT_EL0 0x34 /* Watchpoint, from lower EL */ 685 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 686 #define EXCP_BRKPT_32 0x38 /* 32bits breakpoint */ 687 #define EXCP_BRK 0x3c /* Breakpoint */ 688 689 /* ESR_EL1 */ 690 #define ESR_EL1_REG MRS_REG_ALT_NAME(ESR_EL1) 691 #define ESR_EL1_op0 3 692 #define ESR_EL1_op1 0 693 #define ESR_EL1_CRn 5 694 #define ESR_EL1_CRm 2 695 #define ESR_EL1_op2 0 696 697 /* ESR_EL12 */ 698 #define ESR_EL12_REG MRS_REG_ALT_NAME(ESR_EL12) 699 #define ESR_EL12_op0 3 700 #define ESR_EL12_op1 5 701 #define ESR_EL12_CRn 5 702 #define ESR_EL12_CRm 2 703 #define ESR_EL12_op2 0 704 705 /* FAR_EL1 */ 706 #define FAR_EL1_REG MRS_REG_ALT_NAME(FAR_EL1) 707 #define FAR_EL1_op0 3 708 #define FAR_EL1_op1 0 709 #define FAR_EL1_CRn 6 710 #define FAR_EL1_CRm 0 711 #define FAR_EL1_op2 0 712 713 /* FAR_EL12 */ 714 #define FAR_EL12_REG MRS_REG_ALT_NAME(FAR_EL12) 715 #define FAR_EL12_op0 3 716 #define FAR_EL12_op1 5 717 #define FAR_EL12_CRn 6 718 #define FAR_EL12_CRm 0 719 #define FAR_EL12_op2 0 720 721 /* ICC_CTLR_EL1 */ 722 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 723 724 /* ICC_IAR1_EL1 */ 725 #define ICC_IAR1_EL1_SPUR (0x03ff) 726 727 /* ICC_IGRPEN0_EL1 */ 728 #define ICC_IGRPEN0_EL1_EN (1U << 0) 729 730 /* ICC_PMR_EL1 */ 731 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 732 733 /* ICC_SGI1R_EL1 */ 734 #define ICC_SGI1R_EL1 MRS_REG(ICC_SGI1R_EL1) 735 #define ICC_SGI1R_EL1_op0 3 736 #define ICC_SGI1R_EL1_op1 0 737 #define ICC_SGI1R_EL1_CRn 12 738 #define ICC_SGI1R_EL1_CRm 11 739 #define ICC_SGI1R_EL1_op2 5 740 #define ICC_SGI1R_EL1_TL_SHIFT 0 741 #define ICC_SGI1R_EL1_TL_MASK (0xffffUL << ICC_SGI1R_EL1_TL_SHIFT) 742 #define ICC_SGI1R_EL1_TL_VAL(x) ((x) & ICC_SGI1R_EL1_TL_MASK) 743 #define ICC_SGI1R_EL1_AFF1_SHIFT 16 744 #define ICC_SGI1R_EL1_AFF1_MASK (0xfful << ICC_SGI1R_EL1_AFF1_SHIFT) 745 #define ICC_SGI1R_EL1_AFF1_VAL(x) ((x) & ICC_SGI1R_EL1_AFF1_MASK) 746 #define ICC_SGI1R_EL1_SGIID_SHIFT 24 747 #define ICC_SGI1R_EL1_SGIID_MASK (0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT) 748 #define ICC_SGI1R_EL1_SGIID_VAL(x) ((x) & ICC_SGI1R_EL1_SGIID_MASK) 749 #define ICC_SGI1R_EL1_AFF2_SHIFT 32 750 #define ICC_SGI1R_EL1_AFF2_MASK (0xfful << ICC_SGI1R_EL1_AFF2_SHIFT) 751 #define ICC_SGI1R_EL1_AFF2_VAL(x) ((x) & ICC_SGI1R_EL1_AFF2_MASK) 752 #define ICC_SGI1R_EL1_RS_SHIFT 44 753 #define ICC_SGI1R_EL1_RS_MASK (0xful << ICC_SGI1R_EL1_RS_SHIFT) 754 #define ICC_SGI1R_EL1_RS_VAL(x) ((x) & ICC_SGI1R_EL1_RS_MASK) 755 #define ICC_SGI1R_EL1_AFF3_SHIFT 48 756 #define ICC_SGI1R_EL1_AFF3_MASK (0xfful << ICC_SGI1R_EL1_AFF3_SHIFT) 757 #define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK) 758 #define ICC_SGI1R_EL1_IRM (0x1UL << 40) 759 760 /* ICC_SRE_EL1 */ 761 #define ICC_SRE_EL1_SRE (1U << 0) 762 763 /* ID_AA64AFR0_EL1 */ 764 #define ID_AA64AFR0_EL1 MRS_REG(ID_AA64AFR0_EL1) 765 #define ID_AA64AFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR0_EL1) 766 #define ID_AA64AFR0_EL1_op0 3 767 #define ID_AA64AFR0_EL1_op1 0 768 #define ID_AA64AFR0_EL1_CRn 0 769 #define ID_AA64AFR0_EL1_CRm 5 770 #define ID_AA64AFR0_EL1_op2 4 771 772 /* ID_AA64AFR1_EL1 */ 773 #define ID_AA64AFR1_EL1 MRS_REG(ID_AA64AFR1_EL1) 774 #define ID_AA64AFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR1_EL1) 775 #define ID_AA64AFR1_EL1_op0 3 776 #define ID_AA64AFR1_EL1_op1 0 777 #define ID_AA64AFR1_EL1_CRn 0 778 #define ID_AA64AFR1_EL1_CRm 5 779 #define ID_AA64AFR1_EL1_op2 5 780 781 /* ID_AA64DFR0_EL1 */ 782 #define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1) 783 #define ID_AA64DFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR0_EL1) 784 #define ID_AA64DFR0_EL1_op0 3 785 #define ID_AA64DFR0_EL1_op1 0 786 #define ID_AA64DFR0_EL1_CRn 0 787 #define ID_AA64DFR0_EL1_CRm 5 788 #define ID_AA64DFR0_EL1_op2 0 789 #define ID_AA64DFR0_DebugVer_SHIFT 0 790 #define ID_AA64DFR0_DebugVer_WIDTH 4 791 #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) 792 #define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) 793 #define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT) 794 #define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT) 795 #define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT) 796 #define ID_AA64DFR0_DebugVer_8_4 (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT) 797 #define ID_AA64DFR0_DebugVer_8_8 (UL(0xa) << ID_AA64DFR0_DebugVer_SHIFT) 798 #define ID_AA64DFR0_TraceVer_SHIFT 4 799 #define ID_AA64DFR0_TraceVer_WIDTH 4 800 #define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT) 801 #define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) 802 #define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT) 803 #define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT) 804 #define ID_AA64DFR0_PMUVer_SHIFT 8 805 #define ID_AA64DFR0_PMUVer_WIDTH 4 806 #define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 807 #define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) 808 #define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT) 809 #define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT) 810 #define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT) 811 #define ID_AA64DFR0_PMUVer_3_4 (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT) 812 #define ID_AA64DFR0_PMUVer_3_5 (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT) 813 #define ID_AA64DFR0_PMUVer_3_7 (UL(0x7) << ID_AA64DFR0_PMUVer_SHIFT) 814 #define ID_AA64DFR0_PMUVer_3_8 (UL(0x8) << ID_AA64DFR0_PMUVer_SHIFT) 815 #define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 816 #define ID_AA64DFR0_BRPs_SHIFT 12 817 #define ID_AA64DFR0_BRPs_WIDTH 4 818 #define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT) 819 #define ID_AA64DFR0_BRPs_VAL(x) \ 820 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1) 821 #define ID_AA64DFR0_PMSS_SHIFT 16 822 #define ID_AA64DFR0_PMSS_WIDTH 4 823 #define ID_AA64DFR0_PMSS_MASK (UL(0xf) << ID_AA64DFR0_PMSS_SHIFT) 824 #define ID_AA64DFR0_PMSS_VAL(x) ((x) & ID_AA64DFR0_PMSS_MASK) 825 #define ID_AA64DFR0_PMSS_NONE (UL(0x0) << ID_AA64DFR0_PMSS_SHIFT) 826 #define ID_AA64DFR0_PMSS_IMPL (UL(0x1) << ID_AA64DFR0_PMSS_SHIFT) 827 #define ID_AA64DFR0_WRPs_SHIFT 20 828 #define ID_AA64DFR0_WRPs_WIDTH 4 829 #define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) 830 #define ID_AA64DFR0_WRPs_VAL(x) \ 831 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) 832 #define ID_AA64DFR0_CTX_CMPs_SHIFT 28 833 #define ID_AA64DFR0_CTX_CMPs_WIDTH 4 834 #define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) 835 #define ID_AA64DFR0_CTX_CMPs_VAL(x) \ 836 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1) 837 #define ID_AA64DFR0_PMSVer_SHIFT 32 838 #define ID_AA64DFR0_PMSVer_WIDTH 4 839 #define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT) 840 #define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) 841 #define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT) 842 #define ID_AA64DFR0_PMSVer_SPE (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) 843 #define ID_AA64DFR0_PMSVer_SPE_1_1 (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT) 844 #define ID_AA64DFR0_PMSVer_SPE_1_2 (UL(0x3) << ID_AA64DFR0_PMSVer_SHIFT) 845 #define ID_AA64DFR0_PMSVer_SPE_1_3 (UL(0x4) << ID_AA64DFR0_PMSVer_SHIFT) 846 #define ID_AA64DFR0_DoubleLock_SHIFT 36 847 #define ID_AA64DFR0_DoubleLock_WIDTH 4 848 #define ID_AA64DFR0_DoubleLock_MASK (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) 849 #define ID_AA64DFR0_DoubleLock_VAL(x) ((x) & ID_AA64DFR0_DoubleLock_MASK) 850 #define ID_AA64DFR0_DoubleLock_IMPL (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT) 851 #define ID_AA64DFR0_DoubleLock_NONE (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) 852 #define ID_AA64DFR0_TraceFilt_SHIFT 40 853 #define ID_AA64DFR0_TraceFilt_WIDTH 4 854 #define ID_AA64DFR0_TraceFilt_MASK (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT) 855 #define ID_AA64DFR0_TraceFilt_VAL(x) ((x) & ID_AA64DFR0_TraceFilt_MASK) 856 #define ID_AA64DFR0_TraceFilt_NONE (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT) 857 #define ID_AA64DFR0_TraceFilt_8_4 (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT) 858 #define ID_AA64DFR0_TraceBuffer_SHIFT 44 859 #define ID_AA64DFR0_TraceBuffer_WIDTH 4 860 #define ID_AA64DFR0_TraceBuffer_MASK (UL(0xf) << ID_AA64DFR0_TraceBuffer_SHIFT) 861 #define ID_AA64DFR0_TraceBuffer_VAL(x) ((x) & ID_AA64DFR0_TraceBuffer_MASK) 862 #define ID_AA64DFR0_TraceBuffer_NONE (UL(0x0) << ID_AA64DFR0_TraceBuffer_SHIFT) 863 #define ID_AA64DFR0_TraceBuffer_IMPL (UL(0x1) << ID_AA64DFR0_TraceBuffer_SHIFT) 864 #define ID_AA64DFR0_MTPMU_SHIFT 48 865 #define ID_AA64DFR0_MTPMU_WIDTH 4 866 #define ID_AA64DFR0_MTPMU_MASK (UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT) 867 #define ID_AA64DFR0_MTPMU_VAL(x) ((x) & ID_AA64DFR0_MTPMU_MASK) 868 #define ID_AA64DFR0_MTPMU_NONE (UL(0x0) << ID_AA64DFR0_MTPMU_SHIFT) 869 #define ID_AA64DFR0_MTPMU_IMPL (UL(0x1) << ID_AA64DFR0_MTPMU_SHIFT) 870 #define ID_AA64DFR0_MTPMU_NONE_MT_RES0 (UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT) 871 #define ID_AA64DFR0_BRBE_SHIFT 52 872 #define ID_AA64DFR0_BRBE_WIDTH 4 873 #define ID_AA64DFR0_BRBE_MASK (UL(0xf) << ID_AA64DFR0_BRBE_SHIFT) 874 #define ID_AA64DFR0_BRBE_VAL(x) ((x) & ID_AA64DFR0_BRBE_MASK) 875 #define ID_AA64DFR0_BRBE_NONE (UL(0x0) << ID_AA64DFR0_BRBE_SHIFT) 876 #define ID_AA64DFR0_BRBE_IMPL (UL(0x1) << ID_AA64DFR0_BRBE_SHIFT) 877 #define ID_AA64DFR0_BRBE_EL3 (UL(0x2) << ID_AA64DFR0_BRBE_SHIFT) 878 #define ID_AA64DFR0_HPMN0_SHIFT 60 879 #define ID_AA64DFR0_HPMN0_WIDTH 4 880 #define ID_AA64DFR0_HPMN0_MASK (UL(0xf) << ID_AA64DFR0_HPMN0_SHIFT) 881 #define ID_AA64DFR0_HPMN0_VAL(x) ((x) & ID_AA64DFR0_HPMN0_MASK) 882 #define ID_AA64DFR0_HPMN0_CONSTR (UL(0x0) << ID_AA64DFR0_HPMN0_SHIFT) 883 #define ID_AA64DFR0_HPMN0_DEFINED (UL(0x1) << ID_AA64DFR0_HPMN0_SHIFT) 884 885 /* ID_AA64DFR1_EL1 */ 886 #define ID_AA64DFR1_EL1 MRS_REG(ID_AA64DFR1_EL1) 887 #define ID_AA64DFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR1_EL1) 888 #define ID_AA64DFR1_EL1_op0 3 889 #define ID_AA64DFR1_EL1_op1 0 890 #define ID_AA64DFR1_EL1_CRn 0 891 #define ID_AA64DFR1_EL1_CRm 5 892 #define ID_AA64DFR1_EL1_op2 1 893 894 /* ID_AA64ISAR0_EL1 */ 895 #define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1) 896 #define ID_AA64ISAR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR0_EL1) 897 #define ID_AA64ISAR0_EL1_op0 3 898 #define ID_AA64ISAR0_EL1_op1 0 899 #define ID_AA64ISAR0_EL1_CRn 0 900 #define ID_AA64ISAR0_EL1_CRm 6 901 #define ID_AA64ISAR0_EL1_op2 0 902 #define ID_AA64ISAR0_AES_SHIFT 4 903 #define ID_AA64ISAR0_AES_WIDTH 4 904 #define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) 905 #define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) 906 #define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT) 907 #define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT) 908 #define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT) 909 #define ID_AA64ISAR0_SHA1_SHIFT 8 910 #define ID_AA64ISAR0_SHA1_WIDTH 4 911 #define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT) 912 #define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 913 #define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT) 914 #define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT) 915 #define ID_AA64ISAR0_SHA2_SHIFT 12 916 #define ID_AA64ISAR0_SHA2_WIDTH 4 917 #define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT) 918 #define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 919 #define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT) 920 #define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT) 921 #define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT) 922 #define ID_AA64ISAR0_CRC32_SHIFT 16 923 #define ID_AA64ISAR0_CRC32_WIDTH 4 924 #define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT) 925 #define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 926 #define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT) 927 #define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT) 928 #define ID_AA64ISAR0_Atomic_SHIFT 20 929 #define ID_AA64ISAR0_Atomic_WIDTH 4 930 #define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT) 931 #define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) 932 #define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT) 933 #define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT) 934 #define ID_AA64ISAR0_TME_SHIFT 24 935 #define ID_AA64ISAR0_TME_WIDTH 4 936 #define ID_AA64ISAR0_TME_MASK (UL(0xf) << ID_AA64ISAR0_TME_SHIFT) 937 #define ID_AA64ISAR0_TME_NONE (UL(0x0) << ID_AA64ISAR0_TME_SHIFT) 938 #define ID_AA64ISAR0_TME_IMPL (UL(0x1) << ID_AA64ISAR0_TME_SHIFT) 939 #define ID_AA64ISAR0_RDM_SHIFT 28 940 #define ID_AA64ISAR0_RDM_WIDTH 4 941 #define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT) 942 #define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) 943 #define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT) 944 #define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT) 945 #define ID_AA64ISAR0_SHA3_SHIFT 32 946 #define ID_AA64ISAR0_SHA3_WIDTH 4 947 #define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT) 948 #define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 949 #define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT) 950 #define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT) 951 #define ID_AA64ISAR0_SM3_SHIFT 36 952 #define ID_AA64ISAR0_SM3_WIDTH 4 953 #define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT) 954 #define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) 955 #define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT) 956 #define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT) 957 #define ID_AA64ISAR0_SM4_SHIFT 40 958 #define ID_AA64ISAR0_SM4_WIDTH 4 959 #define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT) 960 #define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) 961 #define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT) 962 #define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT) 963 #define ID_AA64ISAR0_DP_SHIFT 44 964 #define ID_AA64ISAR0_DP_WIDTH 4 965 #define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT) 966 #define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) 967 #define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT) 968 #define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) 969 #define ID_AA64ISAR0_FHM_SHIFT 48 970 #define ID_AA64ISAR0_FHM_WIDTH 4 971 #define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT) 972 #define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK) 973 #define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT) 974 #define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT) 975 #define ID_AA64ISAR0_TS_SHIFT 52 976 #define ID_AA64ISAR0_TS_WIDTH 4 977 #define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT) 978 #define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK) 979 #define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT) 980 #define ID_AA64ISAR0_TS_CondM_8_4 (UL(0x1) << ID_AA64ISAR0_TS_SHIFT) 981 #define ID_AA64ISAR0_TS_CondM_8_5 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT) 982 #define ID_AA64ISAR0_TLB_SHIFT 56 983 #define ID_AA64ISAR0_TLB_WIDTH 4 984 #define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT) 985 #define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK) 986 #define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT) 987 #define ID_AA64ISAR0_TLB_TLBIOS (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT) 988 #define ID_AA64ISAR0_TLB_TLBIOSR (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT) 989 #define ID_AA64ISAR0_RNDR_SHIFT 60 990 #define ID_AA64ISAR0_RNDR_WIDTH 4 991 #define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT) 992 #define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK) 993 #define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT) 994 #define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT) 995 996 /* ID_AA64ISAR1_EL1 */ 997 #define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1) 998 #define ID_AA64ISAR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR1_EL1) 999 #define ID_AA64ISAR1_EL1_op0 3 1000 #define ID_AA64ISAR1_EL1_op1 0 1001 #define ID_AA64ISAR1_EL1_CRn 0 1002 #define ID_AA64ISAR1_EL1_CRm 6 1003 #define ID_AA64ISAR1_EL1_op2 1 1004 #define ID_AA64ISAR1_DPB_SHIFT 0 1005 #define ID_AA64ISAR1_DPB_WIDTH 4 1006 #define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) 1007 #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) 1008 #define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT) 1009 #define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT) 1010 #define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT) 1011 #define ID_AA64ISAR1_APA_SHIFT 4 1012 #define ID_AA64ISAR1_APA_WIDTH 4 1013 #define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT) 1014 #define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) 1015 #define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT) 1016 #define ID_AA64ISAR1_APA_PAC (UL(0x1) << ID_AA64ISAR1_APA_SHIFT) 1017 #define ID_AA64ISAR1_APA_EPAC (UL(0x2) << ID_AA64ISAR1_APA_SHIFT) 1018 #define ID_AA64ISAR1_APA_EPAC2 (UL(0x3) << ID_AA64ISAR1_APA_SHIFT) 1019 #define ID_AA64ISAR1_APA_FPAC (UL(0x4) << ID_AA64ISAR1_APA_SHIFT) 1020 #define ID_AA64ISAR1_APA_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_APA_SHIFT) 1021 #define ID_AA64ISAR1_API_SHIFT 8 1022 #define ID_AA64ISAR1_API_WIDTH 4 1023 #define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT) 1024 #define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) 1025 #define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT) 1026 #define ID_AA64ISAR1_API_PAC (UL(0x1) << ID_AA64ISAR1_API_SHIFT) 1027 #define ID_AA64ISAR1_API_EPAC (UL(0x2) << ID_AA64ISAR1_API_SHIFT) 1028 #define ID_AA64ISAR1_API_EPAC2 (UL(0x3) << ID_AA64ISAR1_API_SHIFT) 1029 #define ID_AA64ISAR1_API_FPAC (UL(0x4) << ID_AA64ISAR1_API_SHIFT) 1030 #define ID_AA64ISAR1_API_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_API_SHIFT) 1031 #define ID_AA64ISAR1_JSCVT_SHIFT 12 1032 #define ID_AA64ISAR1_JSCVT_WIDTH 4 1033 #define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT) 1034 #define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 1035 #define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT) 1036 #define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT) 1037 #define ID_AA64ISAR1_FCMA_SHIFT 16 1038 #define ID_AA64ISAR1_FCMA_WIDTH 4 1039 #define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT) 1040 #define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 1041 #define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT) 1042 #define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT) 1043 #define ID_AA64ISAR1_LRCPC_SHIFT 20 1044 #define ID_AA64ISAR1_LRCPC_WIDTH 4 1045 #define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT) 1046 #define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 1047 #define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT) 1048 #define ID_AA64ISAR1_LRCPC_RCPC_8_3 (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT) 1049 #define ID_AA64ISAR1_LRCPC_RCPC_8_4 (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT) 1050 #define ID_AA64ISAR1_GPA_SHIFT 24 1051 #define ID_AA64ISAR1_GPA_WIDTH 4 1052 #define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT) 1053 #define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) 1054 #define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT) 1055 #define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT) 1056 #define ID_AA64ISAR1_GPI_SHIFT 28 1057 #define ID_AA64ISAR1_GPI_WIDTH 4 1058 #define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT) 1059 #define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) 1060 #define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT) 1061 #define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) 1062 #define ID_AA64ISAR1_FRINTTS_SHIFT 32 1063 #define ID_AA64ISAR1_FRINTTS_WIDTH 4 1064 #define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT) 1065 #define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) 1066 #define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT) 1067 #define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT) 1068 #define ID_AA64ISAR1_SB_SHIFT 36 1069 #define ID_AA64ISAR1_SB_WIDTH 4 1070 #define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT) 1071 #define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK) 1072 #define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT) 1073 #define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT) 1074 #define ID_AA64ISAR1_SPECRES_SHIFT 40 1075 #define ID_AA64ISAR1_SPECRES_WIDTH 4 1076 #define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT) 1077 #define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) 1078 #define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT) 1079 #define ID_AA64ISAR1_SPECRES_IMPL (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT) 1080 #define ID_AA64ISAR1_BF16_SHIFT 44 1081 #define ID_AA64ISAR1_BF16_WIDTH 4 1082 #define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT) 1083 #define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) 1084 #define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT) 1085 #define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT) 1086 #define ID_AA64ISAR1_BF16_EBF (UL(0x2) << ID_AA64ISAR1_BF16_SHIFT) 1087 #define ID_AA64ISAR1_DGH_SHIFT 48 1088 #define ID_AA64ISAR1_DGH_WIDTH 4 1089 #define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT) 1090 #define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) 1091 #define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT) 1092 #define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT) 1093 #define ID_AA64ISAR1_I8MM_SHIFT 52 1094 #define ID_AA64ISAR1_I8MM_WIDTH 4 1095 #define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT) 1096 #define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) 1097 #define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) 1098 #define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) 1099 #define ID_AA64ISAR1_XS_SHIFT 56 1100 #define ID_AA64ISAR1_XS_WIDTH 4 1101 #define ID_AA64ISAR1_XS_MASK (UL(0xf) << ID_AA64ISAR1_XS_SHIFT) 1102 #define ID_AA64ISAR1_XS_VAL(x) ((x) & ID_AA64ISAR1_XS_MASK) 1103 #define ID_AA64ISAR1_XS_NONE (UL(0x0) << ID_AA64ISAR1_XS_SHIFT) 1104 #define ID_AA64ISAR1_XS_IMPL (UL(0x1) << ID_AA64ISAR1_XS_SHIFT) 1105 #define ID_AA64ISAR1_LS64_SHIFT 60 1106 #define ID_AA64ISAR1_LS64_WIDTH 4 1107 #define ID_AA64ISAR1_LS64_MASK (UL(0xf) << ID_AA64ISAR1_LS64_SHIFT) 1108 #define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK) 1109 #define ID_AA64ISAR1_LS64_NONE (UL(0x0) << ID_AA64ISAR1_LS64_SHIFT) 1110 #define ID_AA64ISAR1_LS64_IMPL (UL(0x1) << ID_AA64ISAR1_LS64_SHIFT) 1111 #define ID_AA64ISAR1_LS64_V (UL(0x2) << ID_AA64ISAR1_LS64_SHIFT) 1112 #define ID_AA64ISAR1_LS64_ACCDATA (UL(0x3) << ID_AA64ISAR1_LS64_SHIFT) 1113 1114 /* ID_AA64ISAR2_EL1 */ 1115 #define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1) 1116 #define ID_AA64ISAR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR2_EL1) 1117 #define ID_AA64ISAR2_EL1_op0 3 1118 #define ID_AA64ISAR2_EL1_op1 0 1119 #define ID_AA64ISAR2_EL1_CRn 0 1120 #define ID_AA64ISAR2_EL1_CRm 6 1121 #define ID_AA64ISAR2_EL1_op2 2 1122 #define ID_AA64ISAR2_WFxT_SHIFT 0 1123 #define ID_AA64ISAR2_WFxT_WIDTH 4 1124 #define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT) 1125 #define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK) 1126 #define ID_AA64ISAR2_WFxT_NONE (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT) 1127 #define ID_AA64ISAR2_WFxT_IMPL (UL(0x1) << ID_AA64ISAR2_WFxT_SHIFT) 1128 #define ID_AA64ISAR2_RPRES_SHIFT 4 1129 #define ID_AA64ISAR2_RPRES_WIDTH 4 1130 #define ID_AA64ISAR2_RPRES_MASK (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT) 1131 #define ID_AA64ISAR2_RPRES_VAL(x) ((x) & ID_AA64ISAR2_RPRES_MASK) 1132 #define ID_AA64ISAR2_RPRES_NONE (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT) 1133 #define ID_AA64ISAR2_RPRES_IMPL (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT) 1134 #define ID_AA64ISAR2_GPA3_SHIFT 8 1135 #define ID_AA64ISAR2_GPA3_WIDTH 4 1136 #define ID_AA64ISAR2_GPA3_MASK (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT) 1137 #define ID_AA64ISAR2_GPA3_VAL(x) ((x) & ID_AA64ISAR2_GPA3_MASK) 1138 #define ID_AA64ISAR2_GPA3_NONE (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT) 1139 #define ID_AA64ISAR2_GPA3_IMPL (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT) 1140 #define ID_AA64ISAR2_APA3_SHIFT 12 1141 #define ID_AA64ISAR2_APA3_WIDTH 4 1142 #define ID_AA64ISAR2_APA3_MASK (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT) 1143 #define ID_AA64ISAR2_APA3_VAL(x) ((x) & ID_AA64ISAR2_APA3_MASK) 1144 #define ID_AA64ISAR2_APA3_NONE (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT) 1145 #define ID_AA64ISAR2_APA3_PAC (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT) 1146 #define ID_AA64ISAR2_APA3_EPAC (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT) 1147 #define ID_AA64ISAR2_APA3_EPAC2 (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT) 1148 #define ID_AA64ISAR2_APA3_FPAC (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT) 1149 #define ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT) 1150 #define ID_AA64ISAR2_MOPS_SHIFT 16 1151 #define ID_AA64ISAR2_MOPS_WIDTH 4 1152 #define ID_AA64ISAR2_MOPS_MASK (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT) 1153 #define ID_AA64ISAR2_MOPS_VAL(x) ((x) & ID_AA64ISAR2_MOPS_MASK) 1154 #define ID_AA64ISAR2_MOPS_NONE (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT) 1155 #define ID_AA64ISAR2_MOPS_IMPL (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT) 1156 #define ID_AA64ISAR2_BC_SHIFT 20 1157 #define ID_AA64ISAR2_BC_WIDTH 4 1158 #define ID_AA64ISAR2_BC_MASK (UL(0xf) << ID_AA64ISAR2_BC_SHIFT) 1159 #define ID_AA64ISAR2_BC_VAL(x) ((x) & ID_AA64ISAR2_BC_MASK) 1160 #define ID_AA64ISAR2_BC_NONE (UL(0x0) << ID_AA64ISAR2_BC_SHIFT) 1161 #define ID_AA64ISAR2_BC_IMPL (UL(0x1) << ID_AA64ISAR2_BC_SHIFT) 1162 #define ID_AA64ISAR2_PAC_frac_SHIFT 28 1163 #define ID_AA64ISAR2_PAC_frac_WIDTH 4 1164 #define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT) 1165 #define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK) 1166 #define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT) 1167 #define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT) 1168 1169 /* ID_AA64MMFR0_EL1 */ 1170 #define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) 1171 #define ID_AA64MMFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR0_EL1) 1172 #define ID_AA64MMFR0_EL1_op0 3 1173 #define ID_AA64MMFR0_EL1_op1 0 1174 #define ID_AA64MMFR0_EL1_CRn 0 1175 #define ID_AA64MMFR0_EL1_CRm 7 1176 #define ID_AA64MMFR0_EL1_op2 0 1177 #define ID_AA64MMFR0_PARange_SHIFT 0 1178 #define ID_AA64MMFR0_PARange_WIDTH 4 1179 #define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) 1180 #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) 1181 #define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT) 1182 #define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT) 1183 #define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT) 1184 #define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT) 1185 #define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT) 1186 #define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT) 1187 #define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT) 1188 #define ID_AA64MMFR0_ASIDBits_SHIFT 4 1189 #define ID_AA64MMFR0_ASIDBits_WIDTH 4 1190 #define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT) 1191 #define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) 1192 #define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT) 1193 #define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT) 1194 #define ID_AA64MMFR0_BigEnd_SHIFT 8 1195 #define ID_AA64MMFR0_BigEnd_WIDTH 4 1196 #define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT) 1197 #define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) 1198 #define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT) 1199 #define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT) 1200 #define ID_AA64MMFR0_SNSMem_SHIFT 12 1201 #define ID_AA64MMFR0_SNSMem_WIDTH 4 1202 #define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT) 1203 #define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) 1204 #define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT) 1205 #define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT) 1206 #define ID_AA64MMFR0_BigEndEL0_SHIFT 16 1207 #define ID_AA64MMFR0_BigEndEL0_WIDTH 4 1208 #define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT) 1209 #define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) 1210 #define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT) 1211 #define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT) 1212 #define ID_AA64MMFR0_TGran16_SHIFT 20 1213 #define ID_AA64MMFR0_TGran16_WIDTH 4 1214 #define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT) 1215 #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) 1216 #define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) 1217 #define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) 1218 #define ID_AA64MMFR0_TGran16_LPA2 (UL(0x2) << ID_AA64MMFR0_TGran16_SHIFT) 1219 #define ID_AA64MMFR0_TGran64_SHIFT 24 1220 #define ID_AA64MMFR0_TGran64_WIDTH 4 1221 #define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 1222 #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) 1223 #define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT) 1224 #define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 1225 #define ID_AA64MMFR0_TGran4_SHIFT 28 1226 #define ID_AA64MMFR0_TGran4_WIDTH 4 1227 #define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 1228 #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) 1229 #define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) 1230 #define ID_AA64MMFR0_TGran4_LPA2 (UL(0x1) << ID_AA64MMFR0_TGran4_SHIFT) 1231 #define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 1232 #define ID_AA64MMFR0_TGran16_2_SHIFT 32 1233 #define ID_AA64MMFR0_TGran16_2_WIDTH 4 1234 #define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT) 1235 #define ID_AA64MMFR0_TGran16_2_VAL(x) ((x) & ID_AA64MMFR0_TGran16_2_MASK) 1236 #define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT) 1237 #define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT) 1238 #define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT) 1239 #define ID_AA64MMFR0_TGran16_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran16_2_SHIFT) 1240 #define ID_AA64MMFR0_TGran64_2_SHIFT 36 1241 #define ID_AA64MMFR0_TGran64_2_WIDTH 4 1242 #define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT) 1243 #define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK) 1244 #define ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT) 1245 #define ID_AA64MMFR0_TGran64_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT) 1246 #define ID_AA64MMFR0_TGran64_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT) 1247 #define ID_AA64MMFR0_TGran4_2_SHIFT 40 1248 #define ID_AA64MMFR0_TGran4_2_WIDTH 4 1249 #define ID_AA64MMFR0_TGran4_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT) 1250 #define ID_AA64MMFR0_TGran4_2_VAL(x) ((x) & ID_AA64MMFR0_TGran4_2_MASK) 1251 #define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT) 1252 #define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT) 1253 #define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT) 1254 #define ID_AA64MMFR0_TGran4_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran4_2_SHIFT) 1255 #define ID_AA64MMFR0_ExS_SHIFT 44 1256 #define ID_AA64MMFR0_ExS_WIDTH 4 1257 #define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT) 1258 #define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK) 1259 #define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT) 1260 #define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT) 1261 #define ID_AA64MMFR0_FGT_SHIFT 56 1262 #define ID_AA64MMFR0_FGT_WIDTH 4 1263 #define ID_AA64MMFR0_FGT_MASK (UL(0xf) << ID_AA64MMFR0_FGT_SHIFT) 1264 #define ID_AA64MMFR0_FGT_VAL(x) ((x) & ID_AA64MMFR0_FGT_MASK) 1265 #define ID_AA64MMFR0_FGT_NONE (UL(0x0) << ID_AA64MMFR0_FGT_SHIFT) 1266 #define ID_AA64MMFR0_FGT_IMPL (UL(0x1) << ID_AA64MMFR0_FGT_SHIFT) 1267 #define ID_AA64MMFR0_ECV_SHIFT 60 1268 #define ID_AA64MMFR0_ECV_WIDTH 4 1269 #define ID_AA64MMFR0_ECV_MASK (UL(0xf) << ID_AA64MMFR0_ECV_SHIFT) 1270 #define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK) 1271 #define ID_AA64MMFR0_ECV_NONE (UL(0x0) << ID_AA64MMFR0_ECV_SHIFT) 1272 #define ID_AA64MMFR0_ECV_IMPL (UL(0x1) << ID_AA64MMFR0_ECV_SHIFT) 1273 #define ID_AA64MMFR0_ECV_CNTHCTL (UL(0x2) << ID_AA64MMFR0_ECV_SHIFT) 1274 1275 /* ID_AA64MMFR1_EL1 */ 1276 #define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1) 1277 #define ID_AA64MMFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR1_EL1) 1278 #define ID_AA64MMFR1_EL1_op0 3 1279 #define ID_AA64MMFR1_EL1_op1 0 1280 #define ID_AA64MMFR1_EL1_CRn 0 1281 #define ID_AA64MMFR1_EL1_CRm 7 1282 #define ID_AA64MMFR1_EL1_op2 1 1283 #define ID_AA64MMFR1_HAFDBS_SHIFT 0 1284 #define ID_AA64MMFR1_HAFDBS_WIDTH 4 1285 #define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) 1286 #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 1287 #define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT) 1288 #define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT) 1289 #define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT) 1290 #define ID_AA64MMFR1_VMIDBits_SHIFT 4 1291 #define ID_AA64MMFR1_VMIDBits_WIDTH 4 1292 #define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT) 1293 #define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) 1294 #define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT) 1295 #define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT) 1296 #define ID_AA64MMFR1_VH_SHIFT 8 1297 #define ID_AA64MMFR1_VH_WIDTH 4 1298 #define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT) 1299 #define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) 1300 #define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT) 1301 #define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT) 1302 #define ID_AA64MMFR1_HPDS_SHIFT 12 1303 #define ID_AA64MMFR1_HPDS_WIDTH 4 1304 #define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT) 1305 #define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 1306 #define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT) 1307 #define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT) 1308 #define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT) 1309 #define ID_AA64MMFR1_LO_SHIFT 16 1310 #define ID_AA64MMFR1_LO_WIDTH 4 1311 #define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT) 1312 #define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) 1313 #define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT) 1314 #define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT) 1315 #define ID_AA64MMFR1_PAN_SHIFT 20 1316 #define ID_AA64MMFR1_PAN_WIDTH 4 1317 #define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT) 1318 #define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) 1319 #define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT) 1320 #define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT) 1321 #define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) 1322 #define ID_AA64MMFR1_PAN_EPAN (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) 1323 #define ID_AA64MMFR1_SpecSEI_SHIFT 24 1324 #define ID_AA64MMFR1_SpecSEI_WIDTH 4 1325 #define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT) 1326 #define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) 1327 #define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT) 1328 #define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT) 1329 #define ID_AA64MMFR1_XNX_SHIFT 28 1330 #define ID_AA64MMFR1_XNX_WIDTH 4 1331 #define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT) 1332 #define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) 1333 #define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT) 1334 #define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT) 1335 #define ID_AA64MMFR1_TWED_SHIFT 32 1336 #define ID_AA64MMFR1_TWED_WIDTH 4 1337 #define ID_AA64MMFR1_TWED_MASK (UL(0xf) << ID_AA64MMFR1_TWED_SHIFT) 1338 #define ID_AA64MMFR1_TWED_VAL(x) ((x) & ID_AA64MMFR1_TWED_MASK) 1339 #define ID_AA64MMFR1_TWED_NONE (UL(0x0) << ID_AA64MMFR1_TWED_SHIFT) 1340 #define ID_AA64MMFR1_TWED_IMPL (UL(0x1) << ID_AA64MMFR1_TWED_SHIFT) 1341 #define ID_AA64MMFR1_ETS_SHIFT 36 1342 #define ID_AA64MMFR1_ETS_WIDTH 4 1343 #define ID_AA64MMFR1_ETS_MASK (UL(0xf) << ID_AA64MMFR1_ETS_SHIFT) 1344 #define ID_AA64MMFR1_ETS_VAL(x) ((x) & ID_AA64MMFR1_ETS_MASK) 1345 #define ID_AA64MMFR1_ETS_NONE (UL(0x0) << ID_AA64MMFR1_ETS_SHIFT) 1346 #define ID_AA64MMFR1_ETS_IMPL (UL(0x1) << ID_AA64MMFR1_ETS_SHIFT) 1347 #define ID_AA64MMFR1_HCX_SHIFT 40 1348 #define ID_AA64MMFR1_HCX_WIDTH 4 1349 #define ID_AA64MMFR1_HCX_MASK (UL(0xf) << ID_AA64MMFR1_HCX_SHIFT) 1350 #define ID_AA64MMFR1_HCX_VAL(x) ((x) & ID_AA64MMFR1_HCX_MASK) 1351 #define ID_AA64MMFR1_HCX_NONE (UL(0x0) << ID_AA64MMFR1_HCX_SHIFT) 1352 #define ID_AA64MMFR1_HCX_IMPL (UL(0x1) << ID_AA64MMFR1_HCX_SHIFT) 1353 #define ID_AA64MMFR1_AFP_SHIFT 44 1354 #define ID_AA64MMFR1_AFP_WIDTH 4 1355 #define ID_AA64MMFR1_AFP_MASK (UL(0xf) << ID_AA64MMFR1_AFP_SHIFT) 1356 #define ID_AA64MMFR1_AFP_VAL(x) ((x) & ID_AA64MMFR1_AFP_MASK) 1357 #define ID_AA64MMFR1_AFP_NONE (UL(0x0) << ID_AA64MMFR1_AFP_SHIFT) 1358 #define ID_AA64MMFR1_AFP_IMPL (UL(0x1) << ID_AA64MMFR1_AFP_SHIFT) 1359 #define ID_AA64MMFR1_nTLBPA_SHIFT 48 1360 #define ID_AA64MMFR1_nTLBPA_WIDTH 4 1361 #define ID_AA64MMFR1_nTLBPA_MASK (UL(0xf) << ID_AA64MMFR1_nTLBPA_SHIFT) 1362 #define ID_AA64MMFR1_nTLBPA_VAL(x) ((x) & ID_AA64MMFR1_nTLBPA_MASK) 1363 #define ID_AA64MMFR1_nTLBPA_NONE (UL(0x0) << ID_AA64MMFR1_nTLBPA_SHIFT) 1364 #define ID_AA64MMFR1_nTLBPA_IMPL (UL(0x1) << ID_AA64MMFR1_nTLBPA_SHIFT) 1365 #define ID_AA64MMFR1_TIDCP1_SHIFT 52 1366 #define ID_AA64MMFR1_TIDCP1_WIDTH 4 1367 #define ID_AA64MMFR1_TIDCP1_MASK (UL(0xf) << ID_AA64MMFR1_TIDCP1_SHIFT) 1368 #define ID_AA64MMFR1_TIDCP1_VAL(x) ((x) & ID_AA64MMFR1_TIDCP1_MASK) 1369 #define ID_AA64MMFR1_TIDCP1_NONE (UL(0x0) << ID_AA64MMFR1_TIDCP1_SHIFT) 1370 #define ID_AA64MMFR1_TIDCP1_IMPL (UL(0x1) << ID_AA64MMFR1_TIDCP1_SHIFT) 1371 #define ID_AA64MMFR1_CMOVW_SHIFT 56 1372 #define ID_AA64MMFR1_CMOVW_WIDTH 4 1373 #define ID_AA64MMFR1_CMOVW_MASK (UL(0xf) << ID_AA64MMFR1_CMOVW_SHIFT) 1374 #define ID_AA64MMFR1_CMOVW_VAL(x) ((x) & ID_AA64MMFR1_CMOVW_MASK) 1375 #define ID_AA64MMFR1_CMOVW_NONE (UL(0x0) << ID_AA64MMFR1_CMOVW_SHIFT) 1376 #define ID_AA64MMFR1_CMOVW_IMPL (UL(0x1) << ID_AA64MMFR1_CMOVW_SHIFT) 1377 1378 /* ID_AA64MMFR2_EL1 */ 1379 #define ID_AA64MMFR2_EL1 MRS_REG(ID_AA64MMFR2_EL1) 1380 #define ID_AA64MMFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR2_EL1) 1381 #define ID_AA64MMFR2_EL1_op0 3 1382 #define ID_AA64MMFR2_EL1_op1 0 1383 #define ID_AA64MMFR2_EL1_CRn 0 1384 #define ID_AA64MMFR2_EL1_CRm 7 1385 #define ID_AA64MMFR2_EL1_op2 2 1386 #define ID_AA64MMFR2_CnP_SHIFT 0 1387 #define ID_AA64MMFR2_CnP_WIDTH 4 1388 #define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) 1389 #define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) 1390 #define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT) 1391 #define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT) 1392 #define ID_AA64MMFR2_UAO_SHIFT 4 1393 #define ID_AA64MMFR2_UAO_WIDTH 4 1394 #define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT) 1395 #define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) 1396 #define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT) 1397 #define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT) 1398 #define ID_AA64MMFR2_LSM_SHIFT 8 1399 #define ID_AA64MMFR2_LSM_WIDTH 4 1400 #define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT) 1401 #define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) 1402 #define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT) 1403 #define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT) 1404 #define ID_AA64MMFR2_IESB_SHIFT 12 1405 #define ID_AA64MMFR2_IESB_WIDTH 4 1406 #define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT) 1407 #define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) 1408 #define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT) 1409 #define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT) 1410 #define ID_AA64MMFR2_VARange_SHIFT 16 1411 #define ID_AA64MMFR2_VARange_WIDTH 4 1412 #define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT) 1413 #define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) 1414 #define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT) 1415 #define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT) 1416 #define ID_AA64MMFR2_CCIDX_SHIFT 20 1417 #define ID_AA64MMFR2_CCIDX_WIDTH 4 1418 #define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT) 1419 #define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 1420 #define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT) 1421 #define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT) 1422 #define ID_AA64MMFR2_NV_SHIFT 24 1423 #define ID_AA64MMFR2_NV_WIDTH 4 1424 #define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT) 1425 #define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) 1426 #define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT) 1427 #define ID_AA64MMFR2_NV_8_3 (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) 1428 #define ID_AA64MMFR2_NV_8_4 (UL(0x2) << ID_AA64MMFR2_NV_SHIFT) 1429 #define ID_AA64MMFR2_ST_SHIFT 28 1430 #define ID_AA64MMFR2_ST_WIDTH 4 1431 #define ID_AA64MMFR2_ST_MASK (UL(0xf) << ID_AA64MMFR2_ST_SHIFT) 1432 #define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK) 1433 #define ID_AA64MMFR2_ST_NONE (UL(0x0) << ID_AA64MMFR2_ST_SHIFT) 1434 #define ID_AA64MMFR2_ST_IMPL (UL(0x1) << ID_AA64MMFR2_ST_SHIFT) 1435 #define ID_AA64MMFR2_AT_SHIFT 32 1436 #define ID_AA64MMFR2_AT_WIDTH 4 1437 #define ID_AA64MMFR2_AT_MASK (UL(0xf) << ID_AA64MMFR2_AT_SHIFT) 1438 #define ID_AA64MMFR2_AT_VAL(x) ((x) & ID_AA64MMFR2_AT_MASK) 1439 #define ID_AA64MMFR2_AT_NONE (UL(0x0) << ID_AA64MMFR2_AT_SHIFT) 1440 #define ID_AA64MMFR2_AT_IMPL (UL(0x1) << ID_AA64MMFR2_AT_SHIFT) 1441 #define ID_AA64MMFR2_IDS_SHIFT 36 1442 #define ID_AA64MMFR2_IDS_WIDTH 4 1443 #define ID_AA64MMFR2_IDS_MASK (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT) 1444 #define ID_AA64MMFR2_IDS_VAL(x) ((x) & ID_AA64MMFR2_IDS_MASK) 1445 #define ID_AA64MMFR2_IDS_NONE (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT) 1446 #define ID_AA64MMFR2_IDS_IMPL (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT) 1447 #define ID_AA64MMFR2_FWB_SHIFT 40 1448 #define ID_AA64MMFR2_FWB_WIDTH 4 1449 #define ID_AA64MMFR2_FWB_MASK (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT) 1450 #define ID_AA64MMFR2_FWB_VAL(x) ((x) & ID_AA64MMFR2_FWB_MASK) 1451 #define ID_AA64MMFR2_FWB_NONE (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT) 1452 #define ID_AA64MMFR2_FWB_IMPL (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT) 1453 #define ID_AA64MMFR2_TTL_SHIFT 48 1454 #define ID_AA64MMFR2_TTL_WIDTH 4 1455 #define ID_AA64MMFR2_TTL_MASK (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT) 1456 #define ID_AA64MMFR2_TTL_VAL(x) ((x) & ID_AA64MMFR2_TTL_MASK) 1457 #define ID_AA64MMFR2_TTL_NONE (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT) 1458 #define ID_AA64MMFR2_TTL_IMPL (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT) 1459 #define ID_AA64MMFR2_BBM_SHIFT 52 1460 #define ID_AA64MMFR2_BBM_WIDTH 4 1461 #define ID_AA64MMFR2_BBM_MASK (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT) 1462 #define ID_AA64MMFR2_BBM_VAL(x) ((x) & ID_AA64MMFR2_BBM_MASK) 1463 #define ID_AA64MMFR2_BBM_LEVEL0 (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT) 1464 #define ID_AA64MMFR2_BBM_LEVEL1 (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT) 1465 #define ID_AA64MMFR2_BBM_LEVEL2 (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT) 1466 #define ID_AA64MMFR2_EVT_SHIFT 56 1467 #define ID_AA64MMFR2_EVT_WIDTH 4 1468 #define ID_AA64MMFR2_EVT_MASK (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT) 1469 #define ID_AA64MMFR2_EVT_VAL(x) ((x) & ID_AA64MMFR2_EVT_MASK) 1470 #define ID_AA64MMFR2_EVT_NONE (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT) 1471 #define ID_AA64MMFR2_EVT_8_2 (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT) 1472 #define ID_AA64MMFR2_EVT_8_5 (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT) 1473 #define ID_AA64MMFR2_E0PD_SHIFT 60 1474 #define ID_AA64MMFR2_E0PD_WIDTH 4 1475 #define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT) 1476 #define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK) 1477 #define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT) 1478 #define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT) 1479 1480 /* ID_AA64MMFR3_EL1 */ 1481 #define ID_AA64MMFR3_EL1 MRS_REG(ID_AA64MMFR3_EL1) 1482 #define ID_AA64MMFR3_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR3_EL1) 1483 #define ID_AA64MMFR3_EL1_op0 3 1484 #define ID_AA64MMFR3_EL1_op1 0 1485 #define ID_AA64MMFR3_EL1_CRn 0 1486 #define ID_AA64MMFR3_EL1_CRm 7 1487 #define ID_AA64MMFR3_EL1_op2 3 1488 #define ID_AA64MMFR3_TCRX_SHIFT 0 1489 #define ID_AA64MMFR3_TCRX_WIDTH 4 1490 #define ID_AA64MMFR3_TCRX_MASK (UL(0xf) << ID_AA64MMFR3_TCRX_SHIFT) 1491 #define ID_AA64MMFR3_TCRX_VAL(x) ((x) & ID_AA64MMFR3_TCRX_MASK) 1492 #define ID_AA64MMFR3_TCRX_NONE (UL(0x0) << ID_AA64MMFR3_TCRX_SHIFT) 1493 #define ID_AA64MMFR3_TCRX_IMPL (UL(0x1) << ID_AA64MMFR3_TCRX_SHIFT) 1494 #define ID_AA64MMFR3_SCTLRX_SHIFT 4 1495 #define ID_AA64MMFR3_SCTLRX_WIDTH 4 1496 #define ID_AA64MMFR3_SCTLRX_MASK (UL(0xf) << ID_AA64MMFR3_SCTLRX_SHIFT) 1497 #define ID_AA64MMFR3_SCTLRX_VAL(x) ((x) & ID_AA64MMFR3_SCTLRX_MASK) 1498 #define ID_AA64MMFR3_SCTLRX_NONE (UL(0x0) << ID_AA64MMFR3_SCTLRX_SHIFT) 1499 #define ID_AA64MMFR3_SCTLRX_IMPL (UL(0x1) << ID_AA64MMFR3_SCTLRX_SHIFT) 1500 #define ID_AA64MMFR3_MEC_SHIFT 28 1501 #define ID_AA64MMFR3_MEC_WIDTH 4 1502 #define ID_AA64MMFR3_MEC_MASK (UL(0xf) << ID_AA64MMFR3_MEC_SHIFT) 1503 #define ID_AA64MMFR3_MEC_VAL(x) ((x) & ID_AA64MMFR3_MEC_MASK) 1504 #define ID_AA64MMFR3_MEC_NONE (UL(0x0) << ID_AA64MMFR3_MEC_SHIFT) 1505 #define ID_AA64MMFR3_MEC_IMPL (UL(0x1) << ID_AA64MMFR3_MEC_SHIFT) 1506 #define ID_AA64MMFR3_Spec_FPACC_SHIFT 60 1507 #define ID_AA64MMFR3_Spec_FPACC_WIDTH 4 1508 #define ID_AA64MMFR3_Spec_FPACC_MASK (UL(0xf) << ID_AA64MMFR3_Spec_FPACC_SHIFT) 1509 #define ID_AA64MMFR3_Spec_FPACC_VAL(x) ((x) & ID_AA64MMFR3_Spec_FPACC_MASK) 1510 #define ID_AA64MMFR3_Spec_FPACC_NONE (UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT) 1511 #define ID_AA64MMFR3_Spec_FPACC_IMPL (UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT) 1512 1513 /* ID_AA64MMFR4_EL1 */ 1514 #define ID_AA64MMFR4_EL1 MRS_REG(ID_AA64MMFR4_EL1) 1515 #define ID_AA64MMFR4_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR4_EL1) 1516 #define ID_AA64MMFR4_EL1_op0 3 1517 #define ID_AA64MMFR4_EL1_op1 0 1518 #define ID_AA64MMFR4_EL1_CRn 0 1519 #define ID_AA64MMFR4_EL1_CRm 7 1520 #define ID_AA64MMFR4_EL1_op2 4 1521 1522 /* ID_AA64PFR0_EL1 */ 1523 #define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1) 1524 #define ID_AA64PFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR0_EL1) 1525 #define ID_AA64PFR0_EL1_op0 3 1526 #define ID_AA64PFR0_EL1_op1 0 1527 #define ID_AA64PFR0_EL1_CRn 0 1528 #define ID_AA64PFR0_EL1_CRm 4 1529 #define ID_AA64PFR0_EL1_op2 0 1530 #define ID_AA64PFR0_EL0_SHIFT 0 1531 #define ID_AA64PFR0_EL0_WIDTH 4 1532 #define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) 1533 #define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) 1534 #define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT) 1535 #define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT) 1536 #define ID_AA64PFR0_EL1_SHIFT 4 1537 #define ID_AA64PFR0_EL1_WIDTH 4 1538 #define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT) 1539 #define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) 1540 #define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT) 1541 #define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT) 1542 #define ID_AA64PFR0_EL2_SHIFT 8 1543 #define ID_AA64PFR0_EL2_WIDTH 4 1544 #define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT) 1545 #define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) 1546 #define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT) 1547 #define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT) 1548 #define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT) 1549 #define ID_AA64PFR0_EL3_SHIFT 12 1550 #define ID_AA64PFR0_EL3_WIDTH 4 1551 #define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT) 1552 #define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) 1553 #define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT) 1554 #define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT) 1555 #define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT) 1556 #define ID_AA64PFR0_FP_SHIFT 16 1557 #define ID_AA64PFR0_FP_WIDTH 4 1558 #define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 1559 #define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) 1560 #define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT) 1561 #define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT) 1562 #define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 1563 #define ID_AA64PFR0_AdvSIMD_SHIFT 20 1564 #define ID_AA64PFR0_AdvSIMD_WIDTH 4 1565 #define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 1566 #define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) 1567 #define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT) 1568 #define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT) 1569 #define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 1570 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 1571 #define ID_AA64PFR0_GIC_SHIFT 24 1572 #define ID_AA64PFR0_GIC_WIDTH 4 1573 #define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT) 1574 #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) 1575 #define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) 1576 #define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) 1577 #define ID_AA64PFR0_GIC_CPUIF_4_1 (UL(0x3) << ID_AA64PFR0_GIC_SHIFT) 1578 #define ID_AA64PFR0_RAS_SHIFT 28 1579 #define ID_AA64PFR0_RAS_WIDTH 4 1580 #define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) 1581 #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) 1582 #define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT) 1583 #define ID_AA64PFR0_RAS_IMPL (UL(0x1) << ID_AA64PFR0_RAS_SHIFT) 1584 #define ID_AA64PFR0_RAS_8_4 (UL(0x2) << ID_AA64PFR0_RAS_SHIFT) 1585 #define ID_AA64PFR0_SVE_SHIFT 32 1586 #define ID_AA64PFR0_SVE_WIDTH 4 1587 #define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT) 1588 #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) 1589 #define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) 1590 #define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) 1591 #define ID_AA64PFR0_SEL2_SHIFT 36 1592 #define ID_AA64PFR0_SEL2_WIDTH 4 1593 #define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT) 1594 #define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) 1595 #define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT) 1596 #define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT) 1597 #define ID_AA64PFR0_MPAM_SHIFT 40 1598 #define ID_AA64PFR0_MPAM_WIDTH 4 1599 #define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT) 1600 #define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) 1601 #define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT) 1602 #define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT) 1603 #define ID_AA64PFR0_AMU_SHIFT 44 1604 #define ID_AA64PFR0_AMU_WIDTH 4 1605 #define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT) 1606 #define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) 1607 #define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT) 1608 #define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT) 1609 #define ID_AA64PFR0_AMU_V1_1 (UL(0x2) << ID_AA64PFR0_AMU_SHIFT) 1610 #define ID_AA64PFR0_DIT_SHIFT 48 1611 #define ID_AA64PFR0_DIT_WIDTH 4 1612 #define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT) 1613 #define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) 1614 #define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT) 1615 #define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT) 1616 #define ID_AA64PFR0_RME_SHIFT 52 1617 #define ID_AA64PFR0_RME_WIDTH 4 1618 #define ID_AA64PFR0_RME_MASK (UL(0xf) << ID_AA64PFR0_RME_SHIFT) 1619 #define ID_AA64PFR0_RME_VAL(x) ((x) & ID_AA64PFR0_RME_MASK) 1620 #define ID_AA64PFR0_RME_NONE (UL(0x0) << ID_AA64PFR0_RME_SHIFT) 1621 #define ID_AA64PFR0_RME_IMPL (UL(0x1) << ID_AA64PFR0_RME_SHIFT) 1622 #define ID_AA64PFR0_CSV2_SHIFT 56 1623 #define ID_AA64PFR0_CSV2_WIDTH 4 1624 #define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT) 1625 #define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) 1626 #define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT) 1627 #define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT) 1628 #define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT) 1629 #define ID_AA64PFR0_CSV2_3 (UL(0x3) << ID_AA64PFR0_CSV2_SHIFT) 1630 #define ID_AA64PFR0_CSV3_SHIFT 60 1631 #define ID_AA64PFR0_CSV3_WIDTH 4 1632 #define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT) 1633 #define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) 1634 #define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT) 1635 #define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT) 1636 1637 /* ID_AA64PFR1_EL1 */ 1638 #define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1) 1639 #define ID_AA64PFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR1_EL1) 1640 #define ID_AA64PFR1_EL1_op0 3 1641 #define ID_AA64PFR1_EL1_op1 0 1642 #define ID_AA64PFR1_EL1_CRn 0 1643 #define ID_AA64PFR1_EL1_CRm 4 1644 #define ID_AA64PFR1_EL1_op2 1 1645 #define ID_AA64PFR1_BT_SHIFT 0 1646 #define ID_AA64PFR1_BT_WIDTH 4 1647 #define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT) 1648 #define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) 1649 #define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT) 1650 #define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT) 1651 #define ID_AA64PFR1_SSBS_SHIFT 4 1652 #define ID_AA64PFR1_SSBS_WIDTH 4 1653 #define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT) 1654 #define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) 1655 #define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT) 1656 #define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT) 1657 #define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT) 1658 #define ID_AA64PFR1_MTE_SHIFT 8 1659 #define ID_AA64PFR1_MTE_WIDTH 4 1660 #define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT) 1661 #define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) 1662 #define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT) 1663 #define ID_AA64PFR1_MTE_MTE (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) 1664 #define ID_AA64PFR1_MTE_MTE2 (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) 1665 #define ID_AA64PFR1_MTE_MTE3 (UL(0x3) << ID_AA64PFR1_MTE_SHIFT) 1666 #define ID_AA64PFR1_RAS_frac_SHIFT 12 1667 #define ID_AA64PFR1_RAS_frac_WIDTH 4 1668 #define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) 1669 #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) 1670 #define ID_AA64PFR1_RAS_frac_p0 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) 1671 #define ID_AA64PFR1_RAS_frac_p1 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) 1672 #define ID_AA64PFR1_MPAM_frac_SHIFT 16 1673 #define ID_AA64PFR1_MPAM_frac_WIDTH 4 1674 #define ID_AA64PFR1_MPAM_frac_MASK (UL(0xf) << ID_AA64PFR1_MPAM_frac_SHIFT) 1675 #define ID_AA64PFR1_MPAM_frac_VAL(x) ((x) & ID_AA64PFR1_MPAM_frac_MASK) 1676 #define ID_AA64PFR1_MPAM_frac_p0 (UL(0x0) << ID_AA64PFR1_MPAM_frac_SHIFT) 1677 #define ID_AA64PFR1_MPAM_frac_p1 (UL(0x1) << ID_AA64PFR1_MPAM_frac_SHIFT) 1678 #define ID_AA64PFR1_SME_SHIFT 24 1679 #define ID_AA64PFR1_SME_WIDTH 4 1680 #define ID_AA64PFR1_SME_MASK (UL(0xf) << ID_AA64PFR1_SME_SHIFT) 1681 #define ID_AA64PFR1_SME_VAL(x) ((x) & ID_AA64PFR1_SME_MASK) 1682 #define ID_AA64PFR1_SME_NONE (UL(0x0) << ID_AA64PFR1_SME_SHIFT) 1683 #define ID_AA64PFR1_SME_SME (UL(0x1) << ID_AA64PFR1_SME_SHIFT) 1684 #define ID_AA64PFR1_SME_SME2 (UL(0x2) << ID_AA64PFR1_SME_SHIFT) 1685 #define ID_AA64PFR1_RNDR_trap_SHIFT 28 1686 #define ID_AA64PFR1_RNDR_trap_WIDTH 4 1687 #define ID_AA64PFR1_RNDR_trap_MASK (UL(0xf) << ID_AA64PFR1_RNDR_trap_SHIFT) 1688 #define ID_AA64PFR1_RNDR_trap_VAL(x) ((x) & ID_AA64PFR1_RNDR_trap_MASK) 1689 #define ID_AA64PFR1_RNDR_trap_NONE (UL(0x0) << ID_AA64PFR1_RNDR_trap_SHIFT) 1690 #define ID_AA64PFR1_RNDR_trap_IMPL (UL(0x1) << ID_AA64PFR1_RNDR_trap_SHIFT) 1691 #define ID_AA64PFR1_CSV2_frac_SHIFT 32 1692 #define ID_AA64PFR1_CSV2_frac_WIDTH 4 1693 #define ID_AA64PFR1_CSV2_frac_MASK (UL(0xf) << ID_AA64PFR1_CSV2_frac_SHIFT) 1694 #define ID_AA64PFR1_CSV2_frac_VAL(x) ((x) & ID_AA64PFR1_CSV2_frac_MASK) 1695 #define ID_AA64PFR1_CSV2_frac_p0 (UL(0x0) << ID_AA64PFR1_CSV2_frac_SHIFT) 1696 #define ID_AA64PFR1_CSV2_frac_p1 (UL(0x1) << ID_AA64PFR1_CSV2_frac_SHIFT) 1697 #define ID_AA64PFR1_CSV2_frac_p2 (UL(0x2) << ID_AA64PFR1_CSV2_frac_SHIFT) 1698 #define ID_AA64PFR1_NMI_SHIFT 36 1699 #define ID_AA64PFR1_NMI_WIDTH 4 1700 #define ID_AA64PFR1_NMI_MASK (UL(0xf) << ID_AA64PFR1_NMI_SHIFT) 1701 #define ID_AA64PFR1_NMI_VAL(x) ((x) & ID_AA64PFR1_NMI_MASK) 1702 #define ID_AA64PFR1_NMI_NONE (UL(0x0) << ID_AA64PFR1_NMI_SHIFT) 1703 #define ID_AA64PFR1_NMI_IMPL (UL(0x1) << ID_AA64PFR1_NMI_SHIFT) 1704 1705 /* ID_AA64PFR2_EL1 */ 1706 #define ID_AA64PFR2_EL1 MRS_REG(ID_AA64PFR2_EL1) 1707 #define ID_AA64PFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR2_EL1) 1708 #define ID_AA64PFR2_EL1_op0 3 1709 #define ID_AA64PFR2_EL1_op1 0 1710 #define ID_AA64PFR2_EL1_CRn 0 1711 #define ID_AA64PFR2_EL1_CRm 4 1712 #define ID_AA64PFR2_EL1_op2 2 1713 1714 /* ID_AA64ZFR0_EL1 */ 1715 #define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1) 1716 #define ID_AA64ZFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1) 1717 #define ID_AA64ZFR0_EL1_op0 3 1718 #define ID_AA64ZFR0_EL1_op1 0 1719 #define ID_AA64ZFR0_EL1_CRn 0 1720 #define ID_AA64ZFR0_EL1_CRm 4 1721 #define ID_AA64ZFR0_EL1_op2 4 1722 #define ID_AA64ZFR0_SVEver_SHIFT 0 1723 #define ID_AA64ZFR0_SVEver_WIDTH 4 1724 #define ID_AA64ZFR0_SVEver_MASK (UL(0xf) << ID_AA64ZFR0_SVEver_SHIFT) 1725 #define ID_AA64ZFR0_SVEver_VAL(x) ((x) & ID_AA64ZFR0_SVEver_MASK 1726 #define ID_AA64ZFR0_SVEver_SVE1 (UL(0x0) << ID_AA64ZFR0_SVEver_SHIFT) 1727 #define ID_AA64ZFR0_SVEver_SVE2 (UL(0x1) << ID_AA64ZFR0_SVEver_SHIFT) 1728 #define ID_AA64ZFR0_SVEver_SVE2P1 (UL(0x2) << ID_AA64ZFR0_SVEver_SHIFT) 1729 #define ID_AA64ZFR0_AES_SHIFT 4 1730 #define ID_AA64ZFR0_AES_WIDTH 4 1731 #define ID_AA64ZFR0_AES_MASK (UL(0xf) << ID_AA64ZFR0_AES_SHIFT) 1732 #define ID_AA64ZFR0_AES_VAL(x) ((x) & ID_AA64ZFR0_AES_MASK 1733 #define ID_AA64ZFR0_AES_NONE (UL(0x0) << ID_AA64ZFR0_AES_SHIFT) 1734 #define ID_AA64ZFR0_AES_BASE (UL(0x1) << ID_AA64ZFR0_AES_SHIFT) 1735 #define ID_AA64ZFR0_AES_PMULL (UL(0x2) << ID_AA64ZFR0_AES_SHIFT) 1736 #define ID_AA64ZFR0_BitPerm_SHIFT 16 1737 #define ID_AA64ZFR0_BitPerm_WIDTH 4 1738 #define ID_AA64ZFR0_BitPerm_MASK (UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT) 1739 #define ID_AA64ZFR0_BitPerm_VAL(x) ((x) & ID_AA64ZFR0_BitPerm_MASK 1740 #define ID_AA64ZFR0_BitPerm_NONE (UL(0x0) << ID_AA64ZFR0_BitPerm_SHIFT) 1741 #define ID_AA64ZFR0_BitPerm_IMPL (UL(0x1) << ID_AA64ZFR0_BitPerm_SHIFT) 1742 #define ID_AA64ZFR0_BF16_SHIFT 20 1743 #define ID_AA64ZFR0_BF16_WIDTH 4 1744 #define ID_AA64ZFR0_BF16_MASK (UL(0xf) << ID_AA64ZFR0_BF16_SHIFT) 1745 #define ID_AA64ZFR0_BF16_VAL(x) ((x) & ID_AA64ZFR0_BF16_MASK 1746 #define ID_AA64ZFR0_BF16_NONE (UL(0x0) << ID_AA64ZFR0_BF16_SHIFT) 1747 #define ID_AA64ZFR0_BF16_BASE (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) 1748 #define ID_AA64ZFR0_BF16_EBF (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) 1749 #define ID_AA64ZFR0_SHA3_SHIFT 32 1750 #define ID_AA64ZFR0_SHA3_WIDTH 4 1751 #define ID_AA64ZFR0_SHA3_MASK (UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT) 1752 #define ID_AA64ZFR0_SHA3_VAL(x) ((x) & ID_AA64ZFR0_SHA3_MASK 1753 #define ID_AA64ZFR0_SHA3_NONE (UL(0x0) << ID_AA64ZFR0_SHA3_SHIFT) 1754 #define ID_AA64ZFR0_SHA3_IMPL (UL(0x1) << ID_AA64ZFR0_SHA3_SHIFT) 1755 #define ID_AA64ZFR0_SM4_SHIFT 40 1756 #define ID_AA64ZFR0_SM4_WIDTH 4 1757 #define ID_AA64ZFR0_SM4_MASK (UL(0xf) << ID_AA64ZFR0_SM4_SHIFT) 1758 #define ID_AA64ZFR0_SM4_VAL(x) ((x) & ID_AA64ZFR0_SM4_MASK 1759 #define ID_AA64ZFR0_SM4_NONE (UL(0x0) << ID_AA64ZFR0_SM4_SHIFT) 1760 #define ID_AA64ZFR0_SM4_IMPL (UL(0x1) << ID_AA64ZFR0_SM4_SHIFT) 1761 #define ID_AA64ZFR0_I8MM_SHIFT 44 1762 #define ID_AA64ZFR0_I8MM_WIDTH 4 1763 #define ID_AA64ZFR0_I8MM_MASK (UL(0xf) << ID_AA64ZFR0_I8MM_SHIFT) 1764 #define ID_AA64ZFR0_I8MM_VAL(x) ((x) & ID_AA64ZFR0_I8MM_MASK 1765 #define ID_AA64ZFR0_I8MM_NONE (UL(0x0) << ID_AA64ZFR0_I8MM_SHIFT) 1766 #define ID_AA64ZFR0_I8MM_IMPL (UL(0x1) << ID_AA64ZFR0_I8MM_SHIFT) 1767 #define ID_AA64ZFR0_F32MM_SHIFT 52 1768 #define ID_AA64ZFR0_F32MM_WIDTH 4 1769 #define ID_AA64ZFR0_F32MM_MASK (UL(0xf) << ID_AA64ZFR0_F32MM_SHIFT) 1770 #define ID_AA64ZFR0_F32MM_VAL(x) ((x) & ID_AA64ZFR0_F32MM_MASK 1771 #define ID_AA64ZFR0_F32MM_NONE (UL(0x0) << ID_AA64ZFR0_F32MM_SHIFT) 1772 #define ID_AA64ZFR0_F32MM_IMPL (UL(0x1) << ID_AA64ZFR0_F32MM_SHIFT) 1773 #define ID_AA64ZFR0_F64MM_SHIFT 56 1774 #define ID_AA64ZFR0_F64MM_WIDTH 4 1775 #define ID_AA64ZFR0_F64MM_MASK (UL(0xf) << ID_AA64ZFR0_F64MM_SHIFT) 1776 #define ID_AA64ZFR0_F64MM_VAL(x) ((x) & ID_AA64ZFR0_F64MM_MASK 1777 #define ID_AA64ZFR0_F64MM_NONE (UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT) 1778 #define ID_AA64ZFR0_F64MM_IMPL (UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT) 1779 1780 /* ID_ISAR5_EL1 */ 1781 #define ID_ISAR5_EL1 MRS_REG(ID_ISAR5_EL1) 1782 #define ID_ISAR5_EL1_op0 0x3 1783 #define ID_ISAR5_EL1_op1 0x0 1784 #define ID_ISAR5_EL1_CRn 0x0 1785 #define ID_ISAR5_EL1_CRm 0x2 1786 #define ID_ISAR5_EL1_op2 0x5 1787 #define ID_ISAR5_SEVL_SHIFT 0 1788 #define ID_ISAR5_SEVL_WIDTH 4 1789 #define ID_ISAR5_SEVL_MASK (UL(0xf) << ID_ISAR5_SEVL_SHIFT) 1790 #define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK) 1791 #define ID_ISAR5_SEVL_NOP (UL(0x0) << ID_ISAR5_SEVL_SHIFT) 1792 #define ID_ISAR5_SEVL_IMPL (UL(0x1) << ID_ISAR5_SEVL_SHIFT) 1793 #define ID_ISAR5_AES_SHIFT 4 1794 #define ID_ISAR5_AES_WIDTH 4 1795 #define ID_ISAR5_AES_MASK (UL(0xf) << ID_ISAR5_AES_SHIFT) 1796 #define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK) 1797 #define ID_ISAR5_AES_NONE (UL(0x0) << ID_ISAR5_AES_SHIFT) 1798 #define ID_ISAR5_AES_BASE (UL(0x1) << ID_ISAR5_AES_SHIFT) 1799 #define ID_ISAR5_AES_VMULL (UL(0x2) << ID_ISAR5_AES_SHIFT) 1800 #define ID_ISAR5_SHA1_SHIFT 8 1801 #define ID_ISAR5_SHA1_WIDTH 4 1802 #define ID_ISAR5_SHA1_MASK (UL(0xf) << ID_ISAR5_SHA1_SHIFT) 1803 #define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK) 1804 #define ID_ISAR5_SHA1_NONE (UL(0x0) << ID_ISAR5_SHA1_SHIFT) 1805 #define ID_ISAR5_SHA1_IMPL (UL(0x1) << ID_ISAR5_SHA1_SHIFT) 1806 #define ID_ISAR5_SHA2_SHIFT 12 1807 #define ID_ISAR5_SHA2_WIDTH 4 1808 #define ID_ISAR5_SHA2_MASK (UL(0xf) << ID_ISAR5_SHA2_SHIFT) 1809 #define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK) 1810 #define ID_ISAR5_SHA2_NONE (UL(0x0) << ID_ISAR5_SHA2_SHIFT) 1811 #define ID_ISAR5_SHA2_IMPL (UL(0x1) << ID_ISAR5_SHA2_SHIFT) 1812 #define ID_ISAR5_CRC32_SHIFT 16 1813 #define ID_ISAR5_CRC32_WIDTH 4 1814 #define ID_ISAR5_CRC32_MASK (UL(0xf) << ID_ISAR5_CRC32_SHIFT) 1815 #define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK) 1816 #define ID_ISAR5_CRC32_NONE (UL(0x0) << ID_ISAR5_CRC32_SHIFT) 1817 #define ID_ISAR5_CRC32_IMPL (UL(0x1) << ID_ISAR5_CRC32_SHIFT) 1818 #define ID_ISAR5_RDM_SHIFT 24 1819 #define ID_ISAR5_RDM_WIDTH 4 1820 #define ID_ISAR5_RDM_MASK (UL(0xf) << ID_ISAR5_RDM_SHIFT) 1821 #define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK) 1822 #define ID_ISAR5_RDM_NONE (UL(0x0) << ID_ISAR5_RDM_SHIFT) 1823 #define ID_ISAR5_RDM_IMPL (UL(0x1) << ID_ISAR5_RDM_SHIFT) 1824 #define ID_ISAR5_VCMA_SHIFT 28 1825 #define ID_ISAR5_VCMA_WIDTH 4 1826 #define ID_ISAR5_VCMA_MASK (UL(0xf) << ID_ISAR5_VCMA_SHIFT) 1827 #define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK) 1828 #define ID_ISAR5_VCMA_NONE (UL(0x0) << ID_ISAR5_VCMA_SHIFT) 1829 #define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT) 1830 1831 /* MAIR_EL1 - Memory Attribute Indirection Register */ 1832 #define MAIR_EL1_REG MRS_REG_ALT_NAME(MAIR_EL1) 1833 #define MAIR_EL1_op0 3 1834 #define MAIR_EL1_op1 0 1835 #define MAIR_EL1_CRn 10 1836 #define MAIR_EL1_CRm 2 1837 #define MAIR_EL1_op2 0 1838 #define MAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8)) 1839 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 1840 #define MAIR_DEVICE_nGnRnE UL(0x00) 1841 #define MAIR_DEVICE_nGnRE UL(0x04) 1842 #define MAIR_NORMAL_NC UL(0x44) 1843 #define MAIR_NORMAL_WT UL(0xbb) 1844 #define MAIR_NORMAL_WB UL(0xff) 1845 1846 /* MAIR_EL12 */ 1847 #define MAIR_EL12_REG MRS_REG_ALT_NAME(MAIR_EL12) 1848 #define MAIR_EL12_op0 3 1849 #define MAIR_EL12_op1 5 1850 #define MAIR_EL12_CRn 10 1851 #define MAIR_EL12_CRm 2 1852 #define MAIR_EL12_op2 0 1853 1854 /* MDCCINT_EL1 */ 1855 #define MDCCINT_EL1 MRS_REG(MDCCINT_EL1) 1856 #define MDCCINT_EL1_op0 2 1857 #define MDCCINT_EL1_op1 0 1858 #define MDCCINT_EL1_CRn 0 1859 #define MDCCINT_EL1_CRm 2 1860 #define MDCCINT_EL1_op2 0 1861 1862 /* MDCCSR_EL0 */ 1863 #define MDCCSR_EL0 MRS_REG(MDCCSR_EL0) 1864 #define MDCCSR_EL0_op0 2 1865 #define MDCCSR_EL0_op1 3 1866 #define MDCCSR_EL0_CRn 0 1867 #define MDCCSR_EL0_CRm 1 1868 #define MDCCSR_EL0_op2 0 1869 1870 /* MDSCR_EL1 - Monitor Debug System Control Register */ 1871 #define MDSCR_EL1 MRS_REG(MDSCR_EL1) 1872 #define MDSCR_EL1_op0 2 1873 #define MDSCR_EL1_op1 0 1874 #define MDSCR_EL1_CRn 0 1875 #define MDSCR_EL1_CRm 2 1876 #define MDSCR_EL1_op2 2 1877 #define MDSCR_SS_SHIFT 0 1878 #define MDSCR_SS (UL(0x1) << MDSCR_SS_SHIFT) 1879 #define MDSCR_KDE_SHIFT 13 1880 #define MDSCR_KDE (UL(0x1) << MDSCR_KDE_SHIFT) 1881 #define MDSCR_MDE_SHIFT 15 1882 #define MDSCR_MDE (UL(0x1) << MDSCR_MDE_SHIFT) 1883 1884 /* MIDR_EL1 - Main ID Register */ 1885 #define MIDR_EL1 MRS_REG(MIDR_EL1) 1886 #define MIDR_EL1_op0 3 1887 #define MIDR_EL1_op1 0 1888 #define MIDR_EL1_CRn 0 1889 #define MIDR_EL1_CRm 0 1890 #define MIDR_EL1_op2 0 1891 1892 /* MPIDR_EL1 - Multiprocessor Affinity Register */ 1893 #define MPIDR_EL1 MRS_REG(MPIDR_EL1) 1894 #define MPIDR_EL1_op0 3 1895 #define MPIDR_EL1_op1 0 1896 #define MPIDR_EL1_CRn 0 1897 #define MPIDR_EL1_CRm 0 1898 #define MPIDR_EL1_op2 5 1899 #define MPIDR_AFF0_SHIFT 0 1900 #define MPIDR_AFF0_MASK (UL(0xff) << MPIDR_AFF0_SHIFT) 1901 #define MPIDR_AFF0_VAL(x) ((x) & MPIDR_AFF0_MASK) 1902 #define MPIDR_AFF1_SHIFT 8 1903 #define MPIDR_AFF1_MASK (UL(0xff) << MPIDR_AFF1_SHIFT) 1904 #define MPIDR_AFF1_VAL(x) ((x) & MPIDR_AFF1_MASK) 1905 #define MPIDR_AFF2_SHIFT 16 1906 #define MPIDR_AFF2_MASK (UL(0xff) << MPIDR_AFF2_SHIFT) 1907 #define MPIDR_AFF2_VAL(x) ((x) & MPIDR_AFF2_MASK) 1908 #define MPIDR_MT_SHIFT 24 1909 #define MPIDR_MT_MASK (UL(0x1) << MPIDR_MT_SHIFT) 1910 #define MPIDR_U_SHIFT 30 1911 #define MPIDR_U_MASK (UL(0x1) << MPIDR_U_SHIFT) 1912 #define MPIDR_AFF3_SHIFT 32 1913 #define MPIDR_AFF3_MASK (UL(0xff) << MPIDR_AFF3_SHIFT) 1914 #define MPIDR_AFF3_VAL(x) ((x) & MPIDR_AFF3_MASK) 1915 1916 /* MVFR0_EL1 */ 1917 #define MVFR0_EL1 MRS_REG(MVFR0_EL1) 1918 #define MVFR0_EL1_op0 0x3 1919 #define MVFR0_EL1_op1 0x0 1920 #define MVFR0_EL1_CRn 0x0 1921 #define MVFR0_EL1_CRm 0x3 1922 #define MVFR0_EL1_op2 0x0 1923 #define MVFR0_SIMDReg_SHIFT 0 1924 #define MVFR0_SIMDReg_WIDTH 4 1925 #define MVFR0_SIMDReg_MASK (UL(0xf) << MVFR0_SIMDReg_SHIFT) 1926 #define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK) 1927 #define MVFR0_SIMDReg_NONE (UL(0x0) << MVFR0_SIMDReg_SHIFT) 1928 #define MVFR0_SIMDReg_FP (UL(0x1) << MVFR0_SIMDReg_SHIFT) 1929 #define MVFR0_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_SIMDReg_SHIFT) 1930 #define MVFR0_FPSP_SHIFT 4 1931 #define MVFR0_FPSP_WIDTH 4 1932 #define MVFR0_FPSP_MASK (UL(0xf) << MVFR0_FPSP_SHIFT) 1933 #define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK) 1934 #define MVFR0_FPSP_NONE (UL(0x0) << MVFR0_FPSP_SHIFT) 1935 #define MVFR0_FPSP_VFP_v2 (UL(0x1) << MVFR0_FPSP_SHIFT) 1936 #define MVFR0_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_FPSP_SHIFT) 1937 #define MVFR0_FPDP_SHIFT 8 1938 #define MVFR0_FPDP_WIDTH 4 1939 #define MVFR0_FPDP_MASK (UL(0xf) << MVFR0_FPDP_SHIFT) 1940 #define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK) 1941 #define MVFR0_FPDP_NONE (UL(0x0) << MVFR0_FPDP_SHIFT) 1942 #define MVFR0_FPDP_VFP_v2 (UL(0x1) << MVFR0_FPDP_SHIFT) 1943 #define MVFR0_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_FPDP_SHIFT) 1944 #define MVFR0_FPTrap_SHIFT 12 1945 #define MVFR0_FPTrap_WIDTH 4 1946 #define MVFR0_FPTrap_MASK (UL(0xf) << MVFR0_FPTrap_SHIFT) 1947 #define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK) 1948 #define MVFR0_FPTrap_NONE (UL(0x0) << MVFR0_FPTrap_SHIFT) 1949 #define MVFR0_FPTrap_IMPL (UL(0x1) << MVFR0_FPTrap_SHIFT) 1950 #define MVFR0_FPDivide_SHIFT 16 1951 #define MVFR0_FPDivide_WIDTH 4 1952 #define MVFR0_FPDivide_MASK (UL(0xf) << MVFR0_FPDivide_SHIFT) 1953 #define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK) 1954 #define MVFR0_FPDivide_NONE (UL(0x0) << MVFR0_FPDivide_SHIFT) 1955 #define MVFR0_FPDivide_IMPL (UL(0x1) << MVFR0_FPDivide_SHIFT) 1956 #define MVFR0_FPSqrt_SHIFT 20 1957 #define MVFR0_FPSqrt_WIDTH 4 1958 #define MVFR0_FPSqrt_MASK (UL(0xf) << MVFR0_FPSqrt_SHIFT) 1959 #define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK) 1960 #define MVFR0_FPSqrt_NONE (UL(0x0) << MVFR0_FPSqrt_SHIFT) 1961 #define MVFR0_FPSqrt_IMPL (UL(0x1) << MVFR0_FPSqrt_SHIFT) 1962 #define MVFR0_FPShVec_SHIFT 24 1963 #define MVFR0_FPShVec_WIDTH 4 1964 #define MVFR0_FPShVec_MASK (UL(0xf) << MVFR0_FPShVec_SHIFT) 1965 #define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK) 1966 #define MVFR0_FPShVec_NONE (UL(0x0) << MVFR0_FPShVec_SHIFT) 1967 #define MVFR0_FPShVec_IMPL (UL(0x1) << MVFR0_FPShVec_SHIFT) 1968 #define MVFR0_FPRound_SHIFT 28 1969 #define MVFR0_FPRound_WIDTH 4 1970 #define MVFR0_FPRound_MASK (UL(0xf) << MVFR0_FPRound_SHIFT) 1971 #define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK) 1972 #define MVFR0_FPRound_NONE (UL(0x0) << MVFR0_FPRound_SHIFT) 1973 #define MVFR0_FPRound_IMPL (UL(0x1) << MVFR0_FPRound_SHIFT) 1974 1975 /* MVFR1_EL1 */ 1976 #define MVFR1_EL1 MRS_REG(MVFR1_EL1) 1977 #define MVFR1_EL1_op0 0x3 1978 #define MVFR1_EL1_op1 0x0 1979 #define MVFR1_EL1_CRn 0x0 1980 #define MVFR1_EL1_CRm 0x3 1981 #define MVFR1_EL1_op2 0x1 1982 #define MVFR1_FPFtZ_SHIFT 0 1983 #define MVFR1_FPFtZ_WIDTH 4 1984 #define MVFR1_FPFtZ_MASK (UL(0xf) << MVFR1_FPFtZ_SHIFT) 1985 #define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK) 1986 #define MVFR1_FPFtZ_NONE (UL(0x0) << MVFR1_FPFtZ_SHIFT) 1987 #define MVFR1_FPFtZ_IMPL (UL(0x1) << MVFR1_FPFtZ_SHIFT) 1988 #define MVFR1_FPDNaN_SHIFT 4 1989 #define MVFR1_FPDNaN_WIDTH 4 1990 #define MVFR1_FPDNaN_MASK (UL(0xf) << MVFR1_FPDNaN_SHIFT) 1991 #define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK) 1992 #define MVFR1_FPDNaN_NONE (UL(0x0) << MVFR1_FPDNaN_SHIFT) 1993 #define MVFR1_FPDNaN_IMPL (UL(0x1) << MVFR1_FPDNaN_SHIFT) 1994 #define MVFR1_SIMDLS_SHIFT 8 1995 #define MVFR1_SIMDLS_WIDTH 4 1996 #define MVFR1_SIMDLS_MASK (UL(0xf) << MVFR1_SIMDLS_SHIFT) 1997 #define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK) 1998 #define MVFR1_SIMDLS_NONE (UL(0x0) << MVFR1_SIMDLS_SHIFT) 1999 #define MVFR1_SIMDLS_IMPL (UL(0x1) << MVFR1_SIMDLS_SHIFT) 2000 #define MVFR1_SIMDInt_SHIFT 12 2001 #define MVFR1_SIMDInt_WIDTH 4 2002 #define MVFR1_SIMDInt_MASK (UL(0xf) << MVFR1_SIMDInt_SHIFT) 2003 #define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK) 2004 #define MVFR1_SIMDInt_NONE (UL(0x0) << MVFR1_SIMDInt_SHIFT) 2005 #define MVFR1_SIMDInt_IMPL (UL(0x1) << MVFR1_SIMDInt_SHIFT) 2006 #define MVFR1_SIMDSP_SHIFT 16 2007 #define MVFR1_SIMDSP_WIDTH 4 2008 #define MVFR1_SIMDSP_MASK (UL(0xf) << MVFR1_SIMDSP_SHIFT) 2009 #define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK) 2010 #define MVFR1_SIMDSP_NONE (UL(0x0) << MVFR1_SIMDSP_SHIFT) 2011 #define MVFR1_SIMDSP_IMPL (UL(0x1) << MVFR1_SIMDSP_SHIFT) 2012 #define MVFR1_SIMDHP_SHIFT 20 2013 #define MVFR1_SIMDHP_WIDTH 4 2014 #define MVFR1_SIMDHP_MASK (UL(0xf) << MVFR1_SIMDHP_SHIFT) 2015 #define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK) 2016 #define MVFR1_SIMDHP_NONE (UL(0x0) << MVFR1_SIMDHP_SHIFT) 2017 #define MVFR1_SIMDHP_CONV_SP (UL(0x1) << MVFR1_SIMDHP_SHIFT) 2018 #define MVFR1_SIMDHP_ARITH (UL(0x2) << MVFR1_SIMDHP_SHIFT) 2019 #define MVFR1_FPHP_SHIFT 24 2020 #define MVFR1_FPHP_WIDTH 4 2021 #define MVFR1_FPHP_MASK (UL(0xf) << MVFR1_FPHP_SHIFT) 2022 #define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK) 2023 #define MVFR1_FPHP_NONE (UL(0x0) << MVFR1_FPHP_SHIFT) 2024 #define MVFR1_FPHP_CONV_SP (UL(0x1) << MVFR1_FPHP_SHIFT) 2025 #define MVFR1_FPHP_CONV_DP (UL(0x2) << MVFR1_FPHP_SHIFT) 2026 #define MVFR1_FPHP_ARITH (UL(0x3) << MVFR1_FPHP_SHIFT) 2027 #define MVFR1_SIMDFMAC_SHIFT 28 2028 #define MVFR1_SIMDFMAC_WIDTH 4 2029 #define MVFR1_SIMDFMAC_MASK (UL(0xf) << MVFR1_SIMDFMAC_SHIFT) 2030 #define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK) 2031 #define MVFR1_SIMDFMAC_NONE (UL(0x0) << MVFR1_SIMDFMAC_SHIFT) 2032 #define MVFR1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_SIMDFMAC_SHIFT) 2033 2034 /* OSDLR_EL1 */ 2035 #define OSDLR_EL1 MRS_REG(OSDLR_EL1) 2036 #define OSDLR_EL1_op0 2 2037 #define OSDLR_EL1_op1 0 2038 #define OSDLR_EL1_CRn 1 2039 #define OSDLR_EL1_CRm 3 2040 #define OSDLR_EL1_op2 4 2041 2042 /* OSLAR_EL1 */ 2043 #define OSLAR_EL1 MRS_REG(OSLAR_EL1) 2044 #define OSLAR_EL1_op0 2 2045 #define OSLAR_EL1_op1 0 2046 #define OSLAR_EL1_CRn 1 2047 #define OSLAR_EL1_CRm 0 2048 #define OSLAR_EL1_op2 4 2049 2050 /* OSLSR_EL1 */ 2051 #define OSLSR_EL1 MRS_REG(OSLSR_EL1) 2052 #define OSLSR_EL1_op0 2 2053 #define OSLSR_EL1_op1 0 2054 #define OSLSR_EL1_CRn 1 2055 #define OSLSR_EL1_CRm 1 2056 #define OSLSR_EL1_op2 4 2057 2058 /* PAR_EL1 - Physical Address Register */ 2059 #define PAR_F_SHIFT 0 2060 #define PAR_F (0x1 << PAR_F_SHIFT) 2061 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 2062 /* When PAR_F == 0 (success) */ 2063 #define PAR_LOW_MASK 0xfff 2064 #define PAR_SH_SHIFT 7 2065 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 2066 #define PAR_NS_SHIFT 9 2067 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 2068 #define PAR_PA_SHIFT 12 2069 #define PAR_PA_MASK 0x0000fffffffff000 2070 #define PAR_ATTR_SHIFT 56 2071 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 2072 /* When PAR_F == 1 (aborted) */ 2073 #define PAR_FST_SHIFT 1 2074 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 2075 #define PAR_PTW_SHIFT 8 2076 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 2077 #define PAR_S_SHIFT 9 2078 #define PAR_S_MASK (0x1 << PAR_S_SHIFT) 2079 2080 /* PMBIDR_EL1 */ 2081 #define PMBIDR_EL1 MRS_REG(PMBIDR_EL1) 2082 #define PMBIDR_EL1_REG MRS_REG_ALT_NAME(PMBIDR_EL1) 2083 #define PMBIDR_EL1_op0 3 2084 #define PMBIDR_EL1_op1 0 2085 #define PMBIDR_EL1_CRn 9 2086 #define PMBIDR_EL1_CRm 10 2087 #define PMBIDR_EL1_op2 7 2088 #define PMBIDR_Align_SHIFT 0 2089 #define PMBIDR_Align_MASK (UL(0xf) << PMBIDR_Align_SHIFT) 2090 #define PMBIDR_P_SHIFT 4 2091 #define PMBIDR_P (UL(0x1) << PMBIDR_P_SHIFT) 2092 #define PMBIDR_F_SHIFT 5 2093 #define PMBIDR_F (UL(0x1) << PMBIDR_F_SHIFT) 2094 2095 /* PMBLIMITR_EL1 */ 2096 #define PMBLIMITR_EL1 MRS_REG(PMBLIMITR_EL1) 2097 #define PMBLIMITR_EL1_REG MRS_REG_ALT_NAME(PMBLIMITR_EL1) 2098 #define PMBLIMITR_EL1_op0 3 2099 #define PMBLIMITR_EL1_op1 0 2100 #define PMBLIMITR_EL1_CRn 9 2101 #define PMBLIMITR_EL1_CRm 10 2102 #define PMBLIMITR_EL1_op2 0 2103 #define PMBLIMITR_E_SHIFT 0 2104 #define PMBLIMITR_E (UL(0x1) << PMBLIMITR_E_SHIFT) 2105 #define PMBLIMITR_FM_SHIFT 1 2106 #define PMBLIMITR_FM_MASK (UL(0x3) << PMBLIMITR_FM_SHIFT) 2107 #define PMBLIMITR_PMFZ_SHIFT 5 2108 #define PMBLIMITR_PMFZ (UL(0x1) << PMBLIMITR_PMFZ_SHIFT) 2109 #define PMBLIMITR_LIMIT_SHIFT 12 2110 #define PMBLIMITR_LIMIT_MASK \ 2111 (UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT) 2112 2113 /* PMBPTR_EL1 */ 2114 #define PMBPTR_EL1 MRS_REG(PMBPTR_EL1) 2115 #define PMBPTR_EL1_REG MRS_REG_ALT_NAME(PMBPTR_EL1) 2116 #define PMBPTR_EL1_op0 3 2117 #define PMBPTR_EL1_op1 0 2118 #define PMBPTR_EL1_CRn 9 2119 #define PMBPTR_EL1_CRm 10 2120 #define PMBPTR_EL1_op2 1 2121 #define PMBPTR_PTR_SHIFT 0 2122 #define PMBPTR_PTR_MASK \ 2123 (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT) 2124 2125 /* PMBSR_EL1 */ 2126 #define PMBSR_EL1 MRS_REG(PMBSR_EL1) 2127 #define PMBSR_EL1_REG MRS_REG_ALT_NAME(PMBSR_EL1) 2128 #define PMBSR_EL1_op0 3 2129 #define PMBSR_EL1_op1 0 2130 #define PMBSR_EL1_CRn 9 2131 #define PMBSR_EL1_CRm 10 2132 #define PMBSR_EL1_op2 3 2133 #define PMBSR_MSS_SHIFT 0 2134 #define PMBSR_MSS_MASK (UL(0xffff) << PMBSR_MSS_SHIFT) 2135 #define PMBSR_MSS_BSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT) 2136 #define PMBSR_MSS_FSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT) 2137 #define PMBSR_COLL_SHIFT 16 2138 #define PMBSR_COLL (UL(0x1) << PMBSR_COLL_SHIFT) 2139 #define PMBSR_S_SHIFT 17 2140 #define PMBSR_S (UL(0x1) << PMBSR_S_SHIFT) 2141 #define PMBSR_EA_SHIFT 18 2142 #define PMBSR_EA (UL(0x1) << PMBSR_EA_SHIFT) 2143 #define PMBSR_DL_SHIFT 19 2144 #define PMBSR_DL (UL(0x1) << PMBSR_DL_SHIFT) 2145 #define PMBSR_EC_SHIFT 26 2146 #define PMBSR_EC_MASK (UL(0x3f) << PMBSR_EC_SHIFT) 2147 2148 /* PMCCFILTR_EL0 */ 2149 #define PMCCFILTR_EL0 MRS_REG(PMCCFILTR_EL0) 2150 #define PMCCFILTR_EL0_op0 3 2151 #define PMCCFILTR_EL0_op1 3 2152 #define PMCCFILTR_EL0_CRn 14 2153 #define PMCCFILTR_EL0_CRm 15 2154 #define PMCCFILTR_EL0_op2 7 2155 2156 /* PMCCNTR_EL0 */ 2157 #define PMCCNTR_EL0 MRS_REG(PMCCNTR_EL0) 2158 #define PMCCNTR_EL0_op0 3 2159 #define PMCCNTR_EL0_op1 3 2160 #define PMCCNTR_EL0_CRn 9 2161 #define PMCCNTR_EL0_CRm 13 2162 #define PMCCNTR_EL0_op2 0 2163 2164 /* PMCEID0_EL0 */ 2165 #define PMCEID0_EL0 MRS_REG(PMCEID0_EL0) 2166 #define PMCEID0_EL0_op0 3 2167 #define PMCEID0_EL0_op1 3 2168 #define PMCEID0_EL0_CRn 9 2169 #define PMCEID0_EL0_CRm 12 2170 #define PMCEID0_EL0_op2 6 2171 2172 /* PMCEID1_EL0 */ 2173 #define PMCEID1_EL0 MRS_REG(PMCEID1_EL0) 2174 #define PMCEID1_EL0_op0 3 2175 #define PMCEID1_EL0_op1 3 2176 #define PMCEID1_EL0_CRn 9 2177 #define PMCEID1_EL0_CRm 12 2178 #define PMCEID1_EL0_op2 7 2179 2180 /* PMCNTENCLR_EL0 */ 2181 #define PMCNTENCLR_EL0 MRS_REG(PMCNTENCLR_EL0) 2182 #define PMCNTENCLR_EL0_op0 3 2183 #define PMCNTENCLR_EL0_op1 3 2184 #define PMCNTENCLR_EL0_CRn 9 2185 #define PMCNTENCLR_EL0_CRm 12 2186 #define PMCNTENCLR_EL0_op2 2 2187 2188 /* PMCNTENSET_EL0 */ 2189 #define PMCNTENSET_EL0 MRS_REG(PMCNTENSET_EL0) 2190 #define PMCNTENSET_EL0_op0 3 2191 #define PMCNTENSET_EL0_op1 3 2192 #define PMCNTENSET_EL0_CRn 9 2193 #define PMCNTENSET_EL0_CRm 12 2194 #define PMCNTENSET_EL0_op2 1 2195 2196 /* PMCR_EL0 - Perfomance Monitoring Counters */ 2197 #define PMCR_EL0 MRS_REG(PMCR_EL0) 2198 #define PMCR_EL0_op0 3 2199 #define PMCR_EL0_op1 3 2200 #define PMCR_EL0_CRn 9 2201 #define PMCR_EL0_CRm 12 2202 #define PMCR_EL0_op2 0 2203 #define PMCR_E (1 << 0) /* Enable all counters */ 2204 #define PMCR_P (1 << 1) /* Reset all counters */ 2205 #define PMCR_C (1 << 2) /* Clock counter reset */ 2206 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 2207 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 2208 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 2209 #define PMCR_LC (1 << 6) /* Long cycle count enable */ 2210 #define PMCR_IMP_SHIFT 24 /* Implementer code */ 2211 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 2212 #define PMCR_IMP_ARM 0x41 2213 #define PMCR_IDCODE_SHIFT 16 /* Identification code */ 2214 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 2215 #define PMCR_IDCODE_CORTEX_A57 0x01 2216 #define PMCR_IDCODE_CORTEX_A72 0x02 2217 #define PMCR_IDCODE_CORTEX_A53 0x03 2218 #define PMCR_IDCODE_CORTEX_A73 0x04 2219 #define PMCR_IDCODE_CORTEX_A35 0x0a 2220 #define PMCR_IDCODE_CORTEX_A76 0x0b 2221 #define PMCR_IDCODE_NEOVERSE_N1 0x0c 2222 #define PMCR_IDCODE_CORTEX_A77 0x10 2223 #define PMCR_IDCODE_CORTEX_A55 0x45 2224 #define PMCR_IDCODE_NEOVERSE_E1 0x46 2225 #define PMCR_IDCODE_CORTEX_A75 0x4a 2226 #define PMCR_N_SHIFT 11 /* Number of counters implemented */ 2227 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 2228 2229 /* PMEVCNTR<n>_EL0 */ 2230 #define PMEVCNTR_EL0_op0 3 2231 #define PMEVCNTR_EL0_op1 3 2232 #define PMEVCNTR_EL0_CRn 14 2233 #define PMEVCNTR_EL0_CRm 8 2234 /* 2235 * PMEVCNTRn_EL0_CRm[1:0] holds the upper 2 bits of 'n' 2236 * PMEVCNTRn_EL0_op2 holds the lower 3 bits of 'n' 2237 */ 2238 2239 /* PMEVTYPER<n>_EL0 - Performance Monitoring Event Type */ 2240 #define PMEVTYPER_EL0_op0 3 2241 #define PMEVTYPER_EL0_op1 3 2242 #define PMEVTYPER_EL0_CRn 14 2243 #define PMEVTYPER_EL0_CRm 12 2244 /* 2245 * PMEVTYPERn_EL0_CRm[1:0] holds the upper 2 bits of 'n' 2246 * PMEVTYPERn_EL0_op2 holds the lower 3 bits of 'n' 2247 */ 2248 #define PMEVTYPER_EVTCOUNT_MASK 0x000003ff /* ARMv8.0 */ 2249 #define PMEVTYPER_EVTCOUNT_8_1_MASK 0x0000ffff /* ARMv8.1+ */ 2250 #define PMEVTYPER_MT (1 << 25) /* Multithreading */ 2251 #define PMEVTYPER_M (1 << 26) /* Secure EL3 filtering */ 2252 #define PMEVTYPER_NSH (1 << 27) /* Non-secure hypervisor filtering */ 2253 #define PMEVTYPER_NSU (1 << 28) /* Non-secure user filtering */ 2254 #define PMEVTYPER_NSK (1 << 29) /* Non-secure kernel filtering */ 2255 #define PMEVTYPER_U (1 << 30) /* User filtering */ 2256 #define PMEVTYPER_P (1 << 31) /* Privileged filtering */ 2257 2258 /* PMINTENCLR_EL1 */ 2259 #define PMINTENCLR_EL1 MRS_REG(PMINTENCLR_EL1) 2260 #define PMINTENCLR_EL1_op0 3 2261 #define PMINTENCLR_EL1_op1 0 2262 #define PMINTENCLR_EL1_CRn 9 2263 #define PMINTENCLR_EL1_CRm 14 2264 #define PMINTENCLR_EL1_op2 2 2265 2266 /* PMINTENSET_EL1 */ 2267 #define PMINTENSET_EL1 MRS_REG(PMINTENSET_EL1) 2268 #define PMINTENSET_EL1_op0 3 2269 #define PMINTENSET_EL1_op1 0 2270 #define PMINTENSET_EL1_CRn 9 2271 #define PMINTENSET_EL1_CRm 14 2272 #define PMINTENSET_EL1_op2 1 2273 2274 /* PMMIR_EL1 */ 2275 #define PMMIR_EL1 MRS_REG(PMMIR_EL1) 2276 #define PMMIR_EL1_op0 3 2277 #define PMMIR_EL1_op1 0 2278 #define PMMIR_EL1_CRn 9 2279 #define PMMIR_EL1_CRm 14 2280 #define PMMIR_EL1_op2 6 2281 2282 /* PMOVSCLR_EL0 */ 2283 #define PMOVSCLR_EL0 MRS_REG(PMOVSCLR_EL0) 2284 #define PMOVSCLR_EL0_op0 3 2285 #define PMOVSCLR_EL0_op1 3 2286 #define PMOVSCLR_EL0_CRn 9 2287 #define PMOVSCLR_EL0_CRm 12 2288 #define PMOVSCLR_EL0_op2 3 2289 2290 /* PMOVSSET_EL0 */ 2291 #define PMOVSSET_EL0 MRS_REG(PMOVSSET_EL0) 2292 #define PMOVSSET_EL0_op0 3 2293 #define PMOVSSET_EL0_op1 3 2294 #define PMOVSSET_EL0_CRn 9 2295 #define PMOVSSET_EL0_CRm 14 2296 #define PMOVSSET_EL0_op2 3 2297 2298 /* PMSCR_EL1 */ 2299 #define PMSCR_EL1 MRS_REG(PMSCR_EL1) 2300 #define PMSCR_EL1_REG MRS_REG_ALT_NAME(PMSCR_EL1) 2301 #define PMSCR_EL1_op0 3 2302 #define PMSCR_EL1_op1 0 2303 #define PMSCR_EL1_CRn 9 2304 #define PMSCR_EL1_CRm 9 2305 #define PMSCR_EL1_op2 0 2306 #define PMSCR_E0SPE_SHIFT 0 2307 #define PMSCR_E0SPE (UL(0x1) << PMSCR_E0SPE_SHIFT) 2308 #define PMSCR_E1SPE_SHIFT 1 2309 #define PMSCR_E1SPE (UL(0x1) << PMSCR_E1SPE_SHIFT) 2310 #define PMSCR_CX_SHIFT 3 2311 #define PMSCR_CX (UL(0x1) << PMSCR_CX_SHIFT) 2312 #define PMSCR_PA_SHIFT 4 2313 #define PMSCR_PA (UL(0x1) << PMSCR_PA_SHIFT) 2314 #define PMSCR_TS_SHIFT 5 2315 #define PMSCR_TS (UL(0x1) << PMSCR_TS_SHIFT) 2316 #define PMSCR_PCT_SHIFT 6 2317 #define PMSCR_PCT_MASK (UL(0x3) << PMSCR_PCT_SHIFT) 2318 2319 /* PMSELR_EL0 */ 2320 #define PMSELR_EL0 MRS_REG(PMSELR_EL0) 2321 #define PMSELR_EL0_op0 3 2322 #define PMSELR_EL0_op1 3 2323 #define PMSELR_EL0_CRn 9 2324 #define PMSELR_EL0_CRm 12 2325 #define PMSELR_EL0_op2 5 2326 #define PMSELR_SEL_MASK 0x1f 2327 2328 /* PMSEVFR_EL1 */ 2329 #define PMSEVFR_EL1 MRS_REG(PMSEVFR_EL1) 2330 #define PMSEVFR_EL1_REG MRS_REG_ALT_NAME(PMSEVFR_EL1) 2331 #define PMSEVFR_EL1_op0 3 2332 #define PMSEVFR_EL1_op1 0 2333 #define PMSEVFR_EL1_CRn 9 2334 #define PMSEVFR_EL1_CRm 9 2335 #define PMSEVFR_EL1_op2 5 2336 2337 /* PMSFCR_EL1 */ 2338 #define PMSFCR_EL1 MRS_REG(PMSFCR_EL1) 2339 #define PMSFCR_EL1_REG MRS_REG_ALT_NAME(PMSFCR_EL1) 2340 #define PMSFCR_EL1_op0 3 2341 #define PMSFCR_EL1_op1 0 2342 #define PMSFCR_EL1_CRn 9 2343 #define PMSFCR_EL1_CRm 9 2344 #define PMSFCR_EL1_op2 4 2345 #define PMSFCR_FE_SHIFT 0 2346 #define PMSFCR_FE (UL(0x1) << PMSFCR_FE_SHIFT) 2347 #define PMSFCR_FT_SHIFT 1 2348 #define PMSFCR_FT (UL(0x1) << PMSFCR_FT_SHIFT) 2349 #define PMSFCR_FL_SHIFT 2 2350 #define PMSFCR_FL (UL(0x1) << PMSFCR_FL_SHIFT) 2351 #define PMSFCR_FnE_SHIFT 3 2352 #define PMSFCR_FnE (UL(0x1) << PMSFCR_FnE_SHIFT) 2353 #define PMSFCR_B_SHIFT 16 2354 #define PMSFCR_B (UL(0x1) << PMSFCR_B_SHIFT) 2355 #define PMSFCR_LD_SHIFT 17 2356 #define PMSFCR_LD (UL(0x1) << PMSFCR_LD_SHIFT) 2357 #define PMSFCR_ST_SHIFT 18 2358 #define PMSFCR_ST (UL(0x1) << PMSFCR_ST_SHIFT) 2359 2360 /* PMSICR_EL1 */ 2361 #define PMSICR_EL1 MRS_REG(PMSICR_EL1) 2362 #define PMSICR_EL1_REG MRS_REG_ALT_NAME(PMSICR_EL1) 2363 #define PMSICR_EL1_op0 3 2364 #define PMSICR_EL1_op1 0 2365 #define PMSICR_EL1_CRn 9 2366 #define PMSICR_EL1_CRm 9 2367 #define PMSICR_EL1_op2 2 2368 #define PMSICR_COUNT_SHIFT 0 2369 #define PMSICR_COUNT_MASK (UL(0xffffffff) << PMSICR_COUNT_SHIFT) 2370 #define PMSICR_ECOUNT_SHIFT 56 2371 #define PMSICR_ECOUNT_MASK (UL(0xff) << PMSICR_ECOUNT_SHIFT) 2372 2373 /* PMSIDR_EL1 */ 2374 #define PMSIDR_EL1 MRS_REG(PMSIDR_EL1) 2375 #define PMSIDR_EL1_REG MRS_REG_ALT_NAME(PMSIDR_EL1) 2376 #define PMSIDR_EL1_op0 3 2377 #define PMSIDR_EL1_op1 0 2378 #define PMSIDR_EL1_CRn 9 2379 #define PMSIDR_EL1_CRm 9 2380 #define PMSIDR_EL1_op2 7 2381 #define PMSIDR_FE_SHIFT 0 2382 #define PMSIDR_FE (UL(0x1) << PMSIDR_FE_SHIFT) 2383 #define PMSIDR_FT_SHIFT 1 2384 #define PMSIDR_FT (UL(0x1) << PMSIDR_FT_SHIFT) 2385 #define PMSIDR_FL_SHIFT 2 2386 #define PMSIDR_FL (UL(0x1) << PMSIDR_FL_SHIFT) 2387 #define PMSIDR_ArchInst_SHIFT 3 2388 #define PMSIDR_ArchInst (UL(0x1) << PMSIDR_ArchInst_SHIFT) 2389 #define PMSIDR_LDS_SHIFT 4 2390 #define PMSIDR_LDS (UL(0x1) << PMSIDR_LDS_SHIFT) 2391 #define PMSIDR_ERnd_SHIFT 5 2392 #define PMSIDR_ERnd (UL(0x1) << PMSIDR_ERnd_SHIFT) 2393 #define PMSIDR_FnE_SHIFT 6 2394 #define PMSIDR_FnE (UL(0x1) << PMSIDR_FnE_SHIFT) 2395 #define PMSIDR_Interval_SHIFT 8 2396 #define PMSIDR_Interval_MASK (UL(0xf) << PMSIDR_Interval_SHIFT) 2397 #define PMSIDR_MaxSize_SHIFT 12 2398 #define PMSIDR_MaxSize_MASK (UL(0xf) << PMSIDR_MaxSize_SHIFT) 2399 #define PMSIDR_CountSize_SHIFT 16 2400 #define PMSIDR_CountSize_MASK (UL(0xf) << PMSIDR_CountSize_SHIFT) 2401 #define PMSIDR_Format_SHIFT 20 2402 #define PMSIDR_Format_MASK (UL(0xf) << PMSIDR_Format_SHIFT) 2403 #define PMSIDR_PBT_SHIFT 24 2404 #define PMSIDR_PBT (UL(0x1) << PMSIDR_PBT_SHIFT) 2405 2406 /* PMSIRR_EL1 */ 2407 #define PMSIRR_EL1 MRS_REG(PMSIRR_EL1) 2408 #define PMSIRR_EL1_REG MRS_REG_ALT_NAME(PMSIRR_EL1) 2409 #define PMSIRR_EL1_op0 3 2410 #define PMSIRR_EL1_op1 0 2411 #define PMSIRR_EL1_CRn 9 2412 #define PMSIRR_EL1_CRm 9 2413 #define PMSIRR_EL1_op2 3 2414 #define PMSIRR_RND_SHIFT 0 2415 #define PMSIRR_RND (UL(0x1) << PMSIRR_RND_SHIFT) 2416 #define PMSIRR_INTERVAL_SHIFT 8 2417 #define PMSIRR_INTERVAL_MASK (UL(0xffffff) << PMSIRR_INTERVAL_SHIFT) 2418 2419 /* PMSLATFR_EL1 */ 2420 #define PMSLATFR_EL1 MRS_REG(PMSLATFR_EL1) 2421 #define PMSLATFR_EL1_REG MRS_REG_ALT_NAME(PMSLATFR_EL1) 2422 #define PMSLATFR_EL1_op0 3 2423 #define PMSLATFR_EL1_op1 0 2424 #define PMSLATFR_EL1_CRn 9 2425 #define PMSLATFR_EL1_CRm 9 2426 #define PMSLATFR_EL1_op2 6 2427 #define PMSLATFR_MINLAT_SHIFT 0 2428 #define PMSLATFR_MINLAT_MASK (UL(0xfff) << PMSLATFR_MINLAT_SHIFT) 2429 2430 /* PMSNEVFR_EL1 */ 2431 #define PMSNEVFR_EL1 MRS_REG(PMSNEVFR_EL1) 2432 #define PMSNEVFR_EL1_REG MRS_REG_ALT_NAME(PMSNEVFR_EL1) 2433 #define PMSNEVFR_EL1_op0 3 2434 #define PMSNEVFR_EL1_op1 0 2435 #define PMSNEVFR_EL1_CRn 9 2436 #define PMSNEVFR_EL1_CRm 9 2437 #define PMSNEVFR_EL1_op2 1 2438 2439 /* PMSWINC_EL0 */ 2440 #define PMSWINC_EL0 MRS_REG(PMSWINC_EL0) 2441 #define PMSWINC_EL0_op0 3 2442 #define PMSWINC_EL0_op1 3 2443 #define PMSWINC_EL0_CRn 9 2444 #define PMSWINC_EL0_CRm 12 2445 #define PMSWINC_EL0_op2 4 2446 2447 /* PMUSERENR_EL0 */ 2448 #define PMUSERENR_EL0 MRS_REG(PMUSERENR_EL0) 2449 #define PMUSERENR_EL0_op0 3 2450 #define PMUSERENR_EL0_op1 3 2451 #define PMUSERENR_EL0_CRn 9 2452 #define PMUSERENR_EL0_CRm 14 2453 #define PMUSERENR_EL0_op2 0 2454 2455 /* PMXEVCNTR_EL0 */ 2456 #define PMXEVCNTR_EL0 MRS_REG(PMXEVCNTR_EL0) 2457 #define PMXEVCNTR_EL0_op0 3 2458 #define PMXEVCNTR_EL0_op1 3 2459 #define PMXEVCNTR_EL0_CRn 9 2460 #define PMXEVCNTR_EL0_CRm 13 2461 #define PMXEVCNTR_EL0_op2 2 2462 2463 /* PMXEVTYPER_EL0 */ 2464 #define PMXEVTYPER_EL0 MRS_REG(PMXEVTYPER_EL0) 2465 #define PMXEVTYPER_EL0_op0 3 2466 #define PMXEVTYPER_EL0_op1 3 2467 #define PMXEVTYPER_EL0_CRn 9 2468 #define PMXEVTYPER_EL0_CRm 13 2469 #define PMXEVTYPER_EL0_op2 1 2470 2471 /* RNDRRS */ 2472 #define RNDRRS MRS_REG(RNDRRS) 2473 #define RNDRRS_REG MRS_REG_ALT_NAME(RNDRRS) 2474 #define RNDRRS_op0 3 2475 #define RNDRRS_op1 3 2476 #define RNDRRS_CRn 2 2477 #define RNDRRS_CRm 4 2478 #define RNDRRS_op2 1 2479 2480 /* SCTLR_EL1 - System Control Register */ 2481 #define SCTLR_EL1_REG MRS_REG_ALT_NAME(SCTLR_EL1) 2482 #define SCTLR_EL1_op0 3 2483 #define SCTLR_EL1_op1 0 2484 #define SCTLR_EL1_CRn 1 2485 #define SCTLR_EL1_CRm 0 2486 #define SCTLR_EL1_op2 0 2487 #define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ 2488 #define SCTLR_M (UL(0x1) << 0) 2489 #define SCTLR_A (UL(0x1) << 1) 2490 #define SCTLR_C (UL(0x1) << 2) 2491 #define SCTLR_SA (UL(0x1) << 3) 2492 #define SCTLR_SA0 (UL(0x1) << 4) 2493 #define SCTLR_CP15BEN (UL(0x1) << 5) 2494 #define SCTLR_nAA (UL(0x1) << 6) 2495 #define SCTLR_ITD (UL(0x1) << 7) 2496 #define SCTLR_SED (UL(0x1) << 8) 2497 #define SCTLR_UMA (UL(0x1) << 9) 2498 #define SCTLR_EnRCTX (UL(0x1) << 10) 2499 #define SCTLR_EOS (UL(0x1) << 11) 2500 #define SCTLR_I (UL(0x1) << 12) 2501 #define SCTLR_EnDB (UL(0x1) << 13) 2502 #define SCTLR_DZE (UL(0x1) << 14) 2503 #define SCTLR_UCT (UL(0x1) << 15) 2504 #define SCTLR_nTWI (UL(0x1) << 16) 2505 /* Bit 17 is reserved */ 2506 #define SCTLR_nTWE (UL(0x1) << 18) 2507 #define SCTLR_WXN (UL(0x1) << 19) 2508 #define SCTLR_TSCXT (UL(0x1) << 20) 2509 #define SCTLR_IESB (UL(0x1) << 21) 2510 #define SCTLR_EIS (UL(0x1) << 22) 2511 #define SCTLR_SPAN (UL(0x1) << 23) 2512 #define SCTLR_E0E (UL(0x1) << 24) 2513 #define SCTLR_EE (UL(0x1) << 25) 2514 #define SCTLR_UCI (UL(0x1) << 26) 2515 #define SCTLR_EnDA (UL(0x1) << 27) 2516 #define SCTLR_nTLSMD (UL(0x1) << 28) 2517 #define SCTLR_LSMAOE (UL(0x1) << 29) 2518 #define SCTLR_EnIB (UL(0x1) << 30) 2519 #define SCTLR_EnIA (UL(0x1) << 31) 2520 /* Bits 34:32 are reserved */ 2521 #define SCTLR_BT0 (UL(0x1) << 35) 2522 #define SCTLR_BT1 (UL(0x1) << 36) 2523 #define SCTLR_ITFSB (UL(0x1) << 37) 2524 #define SCTLR_TCF0_MASK (UL(0x3) << 38) 2525 #define SCTLR_TCF_MASK (UL(0x3) << 40) 2526 #define SCTLR_ATA0 (UL(0x1) << 42) 2527 #define SCTLR_ATA (UL(0x1) << 43) 2528 #define SCTLR_DSSBS (UL(0x1) << 44) 2529 #define SCTLR_TWEDEn (UL(0x1) << 45) 2530 #define SCTLR_TWEDEL_MASK (UL(0xf) << 46) 2531 /* Bits 53:50 are reserved */ 2532 #define SCTLR_EnASR (UL(0x1) << 54) 2533 #define SCTLR_EnAS0 (UL(0x1) << 55) 2534 #define SCTLR_EnALS (UL(0x1) << 56) 2535 #define SCTLR_EPAN (UL(0x1) << 57) 2536 2537 /* SCTLR_EL12 */ 2538 #define SCTLR_EL12_REG MRS_REG_ALT_NAME(SCTLR_EL12) 2539 #define SCTLR_EL12_op0 3 2540 #define SCTLR_EL12_op1 5 2541 #define SCTLR_EL12_CRn 1 2542 #define SCTLR_EL12_CRm 0 2543 #define SCTLR_EL12_op2 0 2544 2545 /* SPSR_EL1 */ 2546 #define SPSR_EL1_REG MRS_REG_ALT_NAME(SPSR_EL1) 2547 #define SPSR_EL1_op0 3 2548 #define SPSR_EL1_op1 0 2549 #define SPSR_EL1_CRn 4 2550 #define SPSR_EL1_CRm 0 2551 #define SPSR_EL1_op2 0 2552 /* 2553 * When the exception is taken in AArch64: 2554 * M[3:2] is the exception level 2555 * M[1] is unused 2556 * M[0] is the SP select: 2557 * 0: always SP0 2558 * 1: current ELs SP 2559 */ 2560 #define PSR_M_EL0t 0x00000000UL 2561 #define PSR_M_EL1t 0x00000004UL 2562 #define PSR_M_EL1h 0x00000005UL 2563 #define PSR_M_EL2t 0x00000008UL 2564 #define PSR_M_EL2h 0x00000009UL 2565 #define PSR_M_64 0x00000000UL 2566 #define PSR_M_32 0x00000010UL 2567 #define PSR_M_MASK 0x0000000fUL 2568 2569 #define PSR_T 0x00000020UL 2570 2571 #define PSR_AARCH32 0x00000010UL 2572 #define PSR_F 0x00000040UL 2573 #define PSR_I 0x00000080UL 2574 #define PSR_A 0x00000100UL 2575 #define PSR_D 0x00000200UL 2576 #define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F) 2577 /* The default DAIF mask. These bits are valid in spsr_el1 and daif */ 2578 #define PSR_DAIF_DEFAULT (0) 2579 #define PSR_DAIF_INTR (PSR_I | PSR_F) 2580 #define PSR_BTYPE 0x00000c00UL 2581 #define PSR_SSBS 0x00001000UL 2582 #define PSR_ALLINT 0x00002000UL 2583 #define PSR_IL 0x00100000UL 2584 #define PSR_SS 0x00200000UL 2585 #define PSR_PAN 0x00400000UL 2586 #define PSR_UAO 0x00800000UL 2587 #define PSR_DIT 0x01000000UL 2588 #define PSR_TCO 0x02000000UL 2589 #define PSR_V 0x10000000UL 2590 #define PSR_C 0x20000000UL 2591 #define PSR_Z 0x40000000UL 2592 #define PSR_N 0x80000000UL 2593 #define PSR_FLAGS 0xf0000000UL 2594 /* PSR fields that can be set from 32-bit and 64-bit processes */ 2595 #define PSR_SETTABLE_32 PSR_FLAGS 2596 #define PSR_SETTABLE_64 (PSR_FLAGS | PSR_SS) 2597 2598 /* SPSR_EL12 */ 2599 #define SPSR_EL12_REG MRS_REG_ALT_NAME(SPSR_EL12) 2600 #define SPSR_EL12_op0 3 2601 #define SPSR_EL12_op1 5 2602 #define SPSR_EL12_CRn 4 2603 #define SPSR_EL12_CRm 0 2604 #define SPSR_EL12_op2 0 2605 2606 /* REVIDR_EL1 - Revision ID Register */ 2607 #define REVIDR_EL1 MRS_REG(REVIDR_EL1) 2608 #define REVIDR_EL1_op0 3 2609 #define REVIDR_EL1_op1 0 2610 #define REVIDR_EL1_CRn 0 2611 #define REVIDR_EL1_CRm 0 2612 #define REVIDR_EL1_op2 6 2613 2614 /* TCR_EL1 - Translation Control Register */ 2615 #define TCR_EL1_REG MRS_REG_ALT_NAME(TCR_EL1) 2616 #define TCR_EL1_op0 3 2617 #define TCR_EL1_op1 0 2618 #define TCR_EL1_CRn 2 2619 #define TCR_EL1_CRm 0 2620 #define TCR_EL1_op2 2 2621 /* Bits 63:59 are reserved */ 2622 #define TCR_DS_SHIFT 59 2623 #define TCR_DS (UL(1) << TCR_DS_SHIFT) 2624 #define TCR_TCMA1_SHIFT 58 2625 #define TCR_TCMA1 (UL(1) << TCR_TCMA1_SHIFT) 2626 #define TCR_TCMA0_SHIFT 57 2627 #define TCR_TCMA0 (UL(1) << TCR_TCMA0_SHIFT) 2628 #define TCR_E0PD1_SHIFT 56 2629 #define TCR_E0PD1 (UL(1) << TCR_E0PD1_SHIFT) 2630 #define TCR_E0PD0_SHIFT 55 2631 #define TCR_E0PD0 (UL(1) << TCR_E0PD0_SHIFT) 2632 #define TCR_NFD1_SHIFT 54 2633 #define TCR_NFD1 (UL(1) << TCR_NFD1_SHIFT) 2634 #define TCR_NFD0_SHIFT 53 2635 #define TCR_NFD0 (UL(1) << TCR_NFD0_SHIFT) 2636 #define TCR_TBID1_SHIFT 52 2637 #define TCR_TBID1 (UL(1) << TCR_TBID1_SHIFT) 2638 #define TCR_TBID0_SHIFT 51 2639 #define TCR_TBID0 (UL(1) << TCR_TBID0_SHIFT) 2640 #define TCR_HWU162_SHIFT 50 2641 #define TCR_HWU162 (UL(1) << TCR_HWU162_SHIFT) 2642 #define TCR_HWU161_SHIFT 49 2643 #define TCR_HWU161 (UL(1) << TCR_HWU161_SHIFT) 2644 #define TCR_HWU160_SHIFT 48 2645 #define TCR_HWU160 (UL(1) << TCR_HWU160_SHIFT) 2646 #define TCR_HWU159_SHIFT 47 2647 #define TCR_HWU159 (UL(1) << TCR_HWU159_SHIFT) 2648 #define TCR_HWU1 \ 2649 (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162) 2650 #define TCR_HWU062_SHIFT 46 2651 #define TCR_HWU062 (UL(1) << TCR_HWU062_SHIFT) 2652 #define TCR_HWU061_SHIFT 45 2653 #define TCR_HWU061 (UL(1) << TCR_HWU061_SHIFT) 2654 #define TCR_HWU060_SHIFT 44 2655 #define TCR_HWU060 (UL(1) << TCR_HWU060_SHIFT) 2656 #define TCR_HWU059_SHIFT 43 2657 #define TCR_HWU059 (UL(1) << TCR_HWU059_SHIFT) 2658 #define TCR_HWU0 \ 2659 (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062) 2660 #define TCR_HPD1_SHIFT 42 2661 #define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT) 2662 #define TCR_HPD0_SHIFT 41 2663 #define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT) 2664 #define TCR_HD_SHIFT 40 2665 #define TCR_HD (UL(1) << TCR_HD_SHIFT) 2666 #define TCR_HA_SHIFT 39 2667 #define TCR_HA (UL(1) << TCR_HA_SHIFT) 2668 #define TCR_TBI1_SHIFT 38 2669 #define TCR_TBI1 (UL(1) << TCR_TBI1_SHIFT) 2670 #define TCR_TBI0_SHIFT 37 2671 #define TCR_TBI0 (UL(1) << TCR_TBI0_SHIFT) 2672 #define TCR_ASID_SHIFT 36 2673 #define TCR_ASID_WIDTH 1 2674 #define TCR_ASID_16 (UL(1) << TCR_ASID_SHIFT) 2675 /* Bit 35 is reserved */ 2676 #define TCR_IPS_SHIFT 32 2677 #define TCR_IPS_WIDTH 3 2678 #define TCR_IPS_32BIT (UL(0) << TCR_IPS_SHIFT) 2679 #define TCR_IPS_36BIT (UL(1) << TCR_IPS_SHIFT) 2680 #define TCR_IPS_40BIT (UL(2) << TCR_IPS_SHIFT) 2681 #define TCR_IPS_42BIT (UL(3) << TCR_IPS_SHIFT) 2682 #define TCR_IPS_44BIT (UL(4) << TCR_IPS_SHIFT) 2683 #define TCR_IPS_48BIT (UL(5) << TCR_IPS_SHIFT) 2684 #define TCR_TG1_SHIFT 30 2685 #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT) 2686 #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT) 2687 #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) 2688 #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) 2689 #define TCR_SH1_SHIFT 28 2690 #define TCR_SH1_IS (UL(3) << TCR_SH1_SHIFT) 2691 #define TCR_ORGN1_SHIFT 26 2692 #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT) 2693 #define TCR_IRGN1_SHIFT 24 2694 #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT) 2695 #define TCR_EPD1_SHIFT 23 2696 #define TCR_EPD1 (UL(1) << TCR_EPD1_SHIFT) 2697 #define TCR_A1_SHIFT 22 2698 #define TCR_A1 (UL(1) << TCR_A1_SHIFT) 2699 #define TCR_T1SZ_SHIFT 16 2700 #define TCR_T1SZ_MASK (UL(0x3f) << TCR_T1SZ_SHIFT) 2701 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 2702 #define TCR_TG0_SHIFT 14 2703 #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) 2704 #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT) 2705 #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT) 2706 #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT) 2707 #define TCR_SH0_SHIFT 12 2708 #define TCR_SH0_IS (UL(3) << TCR_SH0_SHIFT) 2709 #define TCR_ORGN0_SHIFT 10 2710 #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT) 2711 #define TCR_IRGN0_SHIFT 8 2712 #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT) 2713 #define TCR_EPD0_SHIFT 7 2714 #define TCR_EPD0 (UL(1) << TCR_EPD0_SHIFT) 2715 /* Bit 6 is reserved */ 2716 #define TCR_T0SZ_SHIFT 0 2717 #define TCR_T0SZ_MASK (UL(0x3f) << TCR_T0SZ_SHIFT) 2718 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 2719 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 2720 2721 /* TCR_EL12 */ 2722 #define TCR_EL12_REG MRS_REG_ALT_NAME(TCR_EL12) 2723 #define TCR_EL12_op0 3 2724 #define TCR_EL12_op1 5 2725 #define TCR_EL12_CRn 2 2726 #define TCR_EL12_CRm 0 2727 #define TCR_EL12_op2 2 2728 2729 /* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */ 2730 #define TTBR_ASID_SHIFT 48 2731 #define TTBR_ASID_MASK (0xfffful << TTBR_ASID_SHIFT) 2732 #define TTBR_BADDR 0x0000fffffffffffeul 2733 #define TTBR_CnP_SHIFT 0 2734 #define TTBR_CnP (1ul << TTBR_CnP_SHIFT) 2735 2736 /* TTBR0_EL1 */ 2737 #define TTBR0_EL1_REG MRS_REG_ALT_NAME(TTBR0_EL1) 2738 #define TTBR0_EL1_op0 3 2739 #define TTBR0_EL1_op1 0 2740 #define TTBR0_EL1_CRn 2 2741 #define TTBR0_EL1_CRm 0 2742 #define TTBR0_EL1_op2 0 2743 2744 /* TTBR0_EL12 */ 2745 #define TTBR0_EL12_REG MRS_REG_ALT_NAME(TTBR0_EL12) 2746 #define TTBR0_EL12_op0 3 2747 #define TTBR0_EL12_op1 5 2748 #define TTBR0_EL12_CRn 2 2749 #define TTBR0_EL12_CRm 0 2750 #define TTBR0_EL12_op2 0 2751 2752 /* TTBR1_EL1 */ 2753 #define TTBR1_EL1_REG MRS_REG_ALT_NAME(TTBR1_EL1) 2754 #define TTBR1_EL1_op0 3 2755 #define TTBR1_EL1_op1 0 2756 #define TTBR1_EL1_CRn 2 2757 #define TTBR1_EL1_CRm 0 2758 #define TTBR1_EL1_op2 1 2759 2760 /* TTBR1_EL12 */ 2761 #define TTBR1_EL12_REG MRS_REG_ALT_NAME(TTBR1_EL12) 2762 #define TTBR1_EL12_op0 3 2763 #define TTBR1_EL12_op1 5 2764 #define TTBR1_EL12_CRn 2 2765 #define TTBR1_EL12_CRm 0 2766 #define TTBR1_EL12_op2 1 2767 2768 /* VBAR_EL1 */ 2769 #define VBAR_EL1_REG MRS_REG_ALT_NAME(VBAR_EL1) 2770 #define VBAR_EL1_op0 3 2771 #define VBAR_EL1_op1 0 2772 #define VBAR_EL1_CRn 12 2773 #define VBAR_EL1_CRm 0 2774 #define VBAR_EL1_op2 0 2775 2776 /* VBAR_EL12 */ 2777 #define VBAR_EL12_REG MRS_REG_ALT_NAME(VBAR_EL12) 2778 #define VBAR_EL12_op0 3 2779 #define VBAR_EL12_op1 5 2780 #define VBAR_EL12_CRn 12 2781 #define VBAR_EL12_CRm 0 2782 #define VBAR_EL12_op2 0 2783 2784 /* ZCR_EL1 - SVE Control Register */ 2785 #define ZCR_EL1 MRS_REG(ZCR_EL1) 2786 #define ZCR_EL1_REG MRS_REG_ALT_NAME(ZCR_EL1) 2787 #define ZCR_EL1_op0 3 2788 #define ZCR_EL1_op1 0 2789 #define ZCR_EL1_CRn 1 2790 #define ZCR_EL1_CRm 2 2791 #define ZCR_EL1_op2 0 2792 #define ZCR_LEN_SHIFT 0 2793 #define ZCR_LEN_MASK (0xf << ZCR_LEN_SHIFT) 2794 #define ZCR_LEN_BYTES(x) ((((x) & ZCR_LEN_MASK) + 1) * 16) 2795 2796 #endif /* !_MACHINE_ARMREG_H_ */ 2797 2798 #endif /* !__arm__ */ 2799