Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL2 (Results 1 – 1 of 1) sorted by relevance
| /freebsd/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_xusbpadctl.c | 224 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364 macro
570 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
573 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
584 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
586 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
626 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
628 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
630 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
642 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
644 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
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