Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1 (Results 1 – 1 of 1) sorted by relevance
| /freebsd/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_xusbpadctl.c | 211 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 macro
580 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
582 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
603 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
607 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
609 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
611 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
613 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
615 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
659 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
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