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Searched refs:X86 (Results 1 – 25 of 250) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaX86.cpp37 case X86::BI__builtin_ia32_vcvttsd2si32: in CheckBuiltinRoundingOrSAE()
38 case X86::BI__builtin_ia32_vcvttsd2si64: in CheckBuiltinRoundingOrSAE()
39 case X86::BI__builtin_ia32_vcvttsd2usi32: in CheckBuiltinRoundingOrSAE()
40 case X86::BI__builtin_ia32_vcvttsd2usi64: in CheckBuiltinRoundingOrSAE()
41 case X86::BI__builtin_ia32_vcvttss2si32: in CheckBuiltinRoundingOrSAE()
42 case X86::BI__builtin_ia32_vcvttss2si64: in CheckBuiltinRoundingOrSAE()
43 case X86::BI__builtin_ia32_vcvttss2usi32: in CheckBuiltinRoundingOrSAE()
44 case X86::BI__builtin_ia32_vcvttss2usi64: in CheckBuiltinRoundingOrSAE()
45 case X86::BI__builtin_ia32_vcvttsh2si32: in CheckBuiltinRoundingOrSAE()
46 case X86::BI__builtin_ia32_vcvttsh2si64: in CheckBuiltinRoundingOrSAE()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstPrinterCommon.cpp37 bool IsCCMPOrCTEST = X86::isCCMPCC(Opc) || X86::isCTESTCC(Opc); in printCondCode()
142 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; in printVPCOMMnemonic()
143 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; in printVPCOMMnemonic()
144 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; in printVPCOMMnemonic()
145 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; in printVPCOMMnemonic()
146 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; in printVPCOMMnemonic()
147 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; in printVPCOMMnemonic()
148 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; in printVPCOMMnemonic()
149 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; in printVPCOMMnemonic()
161 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: in printVPCMPMnemonic()
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H A DX86ATTInstPrinter.cpp73 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
74 (STI.hasFeature(X86::Is64Bit))) { in printInst()
83 else if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
84 STI.hasFeature(X86::Is16Bit)) { in printInst()
108 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
109 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
110 case X86::CMPSDrmi: case X86::CMPSDrri: in printVecCompareInstr()
111 case X86::CMPSDrmi_Int: case X86::CMPSDrri_Int: in printVecCompareInstr()
112 case X86::CMPSSrmi: case X86::CMPSSrri: in printVecCompareInstr()
113 case X86::CMPSSrmi_Int: case X86::CMPSSrri_Int: in printVecCompareInstr()
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H A DX86IntelInstPrinter.cpp46 if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
47 STI.hasFeature(X86::Is16Bit)) { in printInst()
72 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
73 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
74 case X86::CMPSDrmi: case X86::CMPSDrri: in printVecCompareInstr()
75 case X86::CMPSDrmi_Int: case X86::CMPSDrri_Int: in printVecCompareInstr()
76 case X86::CMPSSrmi: case X86::CMPSSrri: in printVecCompareInstr()
77 case X86::CMPSSrmi_Int: case X86::CMPSSrri_Int: in printVecCompareInstr()
99 case X86::VCMPPDrmi: case X86::VCMPPDrri: in printVecCompareInstr()
100 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: in printVecCompareInstr()
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H A DX86BaseInfo.h25 namespace X86 {
131 case X86::TEST16i16: in classifyFirstOpcodeInMacroFusion()
132 case X86::TEST16mr: in classifyFirstOpcodeInMacroFusion()
133 case X86::TEST16ri: in classifyFirstOpcodeInMacroFusion()
134 case X86::TEST16rr: in classifyFirstOpcodeInMacroFusion()
135 case X86::TEST32i32: in classifyFirstOpcodeInMacroFusion()
136 case X86::TEST32mr: in classifyFirstOpcodeInMacroFusion()
137 case X86::TEST32ri: in classifyFirstOpcodeInMacroFusion()
138 case X86::TEST32rr: in classifyFirstOpcodeInMacroFusion()
139 case X86::TEST64i32: in classifyFirstOpcodeInMacroFusion()
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H A DX86MCTargetDesc.cpp74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in isMemOperand()
79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand()
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand()
91 if (STI.hasFeature(X86::Is16Bit) && Base.isReg() && !Base.getReg() && in is16BitMemOperand()
94 return isMemOperand(MI, Op, X86::GR16RegClassID); in is16BitMemOperand()
98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand()
100 if (Base.isReg() && Base.getReg() == X86::EIP) { in is32BitMemOperand()
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H A DX86ELFObjectWriter.cpp42 unsigned getRelocType32(SMLoc Loc, X86::Specifier Specifier,
45 unsigned getRelocType64(SMLoc Loc, X86::Specifier Specifier,
60 static X86_64RelType getType64(MCFixupKind Kind, X86::Specifier &Specifier, in getType64()
69 case X86::reloc_signed_4byte: in getType64()
70 case X86::reloc_signed_4byte_relax: in getType64()
71 if (Specifier == X86::S_None && !IsPCRel) in getType64()
74 case X86::reloc_global_offset_table: in getType64()
75 Specifier = X86::S_GOT; in getType64()
79 case X86::reloc_riprel_4byte: in getType64()
80 case X86::reloc_riprel_4byte_relax: in getType64()
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H A DX86MCAsmInfo.cpp39 {X86::S_ABS8, "ABS8"},
40 {X86::S_DTPOFF, "DTPOFF"},
41 {X86::S_DTPREL, "DTPREL"},
42 {X86::S_GOT, "GOT"},
43 {X86::S_GOTENT, "GOTENT"},
44 {X86::S_GOTNTPOFF, "GOTNTPOFF"},
45 {X86::S_GOTOFF, "GOTOFF"},
46 {X86::S_GOTPCREL, "GOTPCREL"},
47 {X86::S_GOTPCREL_NORELAX, "GOTPCREL_NORELAX"},
48 {X86::S_GOTREL, "GOTREL"},
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupInstTuning.cpp281 case X86::BLENDPDrri: in processInstruction()
282 return ProcessBLENDToMOV(X86::MOVSDrr, 0x3, 0x1); in processInstruction()
283 case X86::VBLENDPDrri: in processInstruction()
284 return ProcessBLENDToMOV(X86::VMOVSDrr, 0x3, 0x1); in processInstruction()
286 case X86::BLENDPSrri: in processInstruction()
287 return ProcessBLENDToMOV(X86::MOVSSrr, 0xF, 0x1) || in processInstruction()
288 ProcessBLENDToMOV(X86::MOVSDrr, 0xF, 0x3); in processInstruction()
289 case X86::VBLENDPSrri: in processInstruction()
290 return ProcessBLENDToMOV(X86::VMOVSSrr, 0xF, 0x1) || in processInstruction()
291 ProcessBLENDToMOV(X86::VMOVSDrr, 0xF, 0x3); in processInstruction()
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H A DX86InstrInfo.cpp87 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
88 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
89 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
90 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
91 X86::CATCHRET, (STI.is64Bit() ? X86::RET64 : X86::RET32)), in X86InstrInfo()
117 case X86::MOVSX16rr8: in isCoalescableExtInstr()
118 case X86::MOVZX16rr8: in isCoalescableExtInstr()
119 case X86::MOVSX32rr8: in isCoalescableExtInstr()
120 case X86::MOVZX32rr8: in isCoalescableExtInstr()
121 case X86::MOVSX64rr8: in isCoalescableExtInstr()
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H A DX86FloatingPoint.cpp129 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); in calcLiveInMask()
130 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in calcLiveInMask()
131 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
203 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
239 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
249 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
293 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
294 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
316 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
317 return Reg - X86::FP0; in getFPReg()
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H A DX86FixupVectorConstants.cpp399 assert(MI.getNumOperands() >= (OperandNo + X86::AddrNumOperands) && in processInstruction()
401 if (auto *C = X86::getConstantFromPool(MI, OperandNo)) { in processInstruction()
417 MI.getOperand(OperandNo + X86::AddrDisp).setIndex(NewCPI); in processInstruction()
437 case X86::MOVAPDrm: in processInstruction()
438 case X86::MOVAPSrm: in processInstruction()
439 case X86::MOVUPDrm: in processInstruction()
440 case X86::MOVUPSrm: { in processInstruction()
443 {X86::MOVSSrm, 1, 32, rebuildZeroUpperCst}, in processInstruction()
444 {HasSSE2 ? X86::MOVSDrm : 0, 1, 64, rebuildZeroUpperCst}}; in processInstruction()
447 case X86::VMOVAPDrm: in processInstruction()
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H A DX86ExpandPseudo.cpp105 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) in INITIALIZE_PASS()
106 .addReg(X86::RIP) in INITIALIZE_PASS()
112 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) in INITIALIZE_PASS()
114 .addReg(X86::R11); in INITIALIZE_PASS()
120 if (!MBB->isLiveIn(X86::EFLAGS)) in INITIALIZE_PASS()
121 MBB->addLiveIn(X86::EFLAGS); in INITIALIZE_PASS()
126 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC); in INITIALIZE_PASS()
141 BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64)) in INITIALIZE_PASS()
154 EmitCondJumpTarget(X86::COND_B, FirstTarget); in INITIALIZE_PASS()
161 EmitCondJumpTarget(X86::COND_B, FirstTarget); in INITIALIZE_PASS()
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H A DX86InstrFoldTables.cpp30 { X86::VANDNPDZ128rr, X86::VANDNPSZ128rmb, TB_BCAST_SS },
31 { X86::VANDNPDZ256rr, X86::VANDNPSZ256rmb, TB_BCAST_SS },
32 { X86::VANDNPDZrr, X86::VANDNPSZrmb, TB_BCAST_SS },
33 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rmb, TB_BCAST_SD },
34 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rmb, TB_BCAST_SD },
35 { X86::VANDNPSZrr, X86::VANDNPDZrmb, TB_BCAST_SD },
36 { X86::VANDPDZ128rr, X86::VANDPSZ128rmb, TB_BCAST_SS },
37 { X86::VANDPDZ256rr, X86::VANDPSZ256rmb, TB_BCAST_SS },
38 { X86::VANDPDZrr, X86::VANDPSZrmb, TB_BCAST_SS },
39 { X86::VANDPSZ128rr, X86::VANDPDZ128rmb, TB_BCAST_SD },
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H A DX86AvoidStoreForwardingBlocks.cpp133 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
134 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
137 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm || in isXMMLoadOpcode()
138 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm || in isXMMLoadOpcode()
139 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm || in isXMMLoadOpcode()
140 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm; in isXMMLoadOpcode()
143 return Opcode == X86::VMOVUPSYrm || Opcode == X86::VMOVAPSYrm || in isYMMLoadOpcode()
144 Opcode == X86::VMOVUPDYrm || Opcode == X86::VMOVAPDYrm || in isYMMLoadOpcode()
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H A DX86DomainReassignment.cpp45 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
61 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
62 return &X86::VK8RegClass; in getDstRC()
63 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
64 return &X86::VK16RegClass; in getDstRC()
65 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
66 return &X86::VK32RegClass; in getDstRC()
67 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
68 return &X86::VK64RegClass; in getDstRC()
215 if (DstReg.isPhysical() && (X86::GR8RegClass.contains(DstReg) || in isLegal()
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H A DX86RegisterInfo.cpp56 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
59 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
76 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
77 FramePtr = Use64BitReg ? X86::RBP : X86::EBP; in X86RegisterInfo()
78 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
81 StackPtr = X86::ESP; in X86RegisterInfo()
82 FramePtr = X86::EBP; in X86RegisterInfo()
83 BasePtr = X86::ESI; in X86RegisterInfo()
92 if (!Is64Bit && Idx == X86::sub_8bit) in getSubClassWithSubReg()
93 Idx = X86::sub_8bit_hi; in getSubClassWithSubReg()
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H A DX86MCInstLower.cpp237 uint16_t Specifier = X86::S_None; in LowerSymbolOperand()
250 Specifier = X86::S_TLVP; in LowerSymbolOperand()
253 Expr = MCSymbolRefExpr::create(Sym, X86::S_TLVP, Ctx); in LowerSymbolOperand()
259 Specifier = uint16_t(X86::S_COFF_SECREL); in LowerSymbolOperand()
262 Specifier = X86::S_TLSGD; in LowerSymbolOperand()
265 Specifier = X86::S_TLSLD; in LowerSymbolOperand()
268 Specifier = X86::S_TLSLDM; in LowerSymbolOperand()
271 Specifier = X86::S_GOTTPOFF; in LowerSymbolOperand()
274 Specifier = X86::S_INDNTPOFF; in LowerSymbolOperand()
277 Specifier = X86::S_TPOFF; in LowerSymbolOperand()
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H A DX86CompressEVEX.cpp89 if (Reg >= X86::XMM16 && Reg <= X86::XMM31) in usesExtendedRegister()
92 if (Reg >= X86::YMM16 && Reg <= X86::YMM31) in usesExtendedRegister()
121 case X86::VALIGNDZ128rri: in performCustomAdjustments()
122 case X86::VALIGNDZ128rmi: in performCustomAdjustments()
123 case X86::VALIGNQZ128rri: in performCustomAdjustments()
124 case X86::VALIGNQZ128rmi: { in performCustomAdjustments()
125 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments()
128 (Opc == X86::VALIGNQZ128rri || Opc == X86::VALIGNQZ128rmi) ? 8 : 4; in performCustomAdjustments()
133 case X86::VSHUFF32X4Z256rmi: in performCustomAdjustments()
134 case X86::VSHUFF32X4Z256rri: in performCustomAdjustments()
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H A DX86EvexToVex.cpp
H A DX86InstructionSelector.cpp
H A DX86FastISel.cpp162 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
220 X86::AddrIndexReg); in addFullAddress()
226 bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I, in foldX86XALUIntrinsic()
246 X86::CondCode TmpCC; in foldX86XALUIntrinsic()
252 case Intrinsic::umul_with_overflow: TmpCC = X86::COND_O; break; in foldX86XALUIntrinsic()
254 case Intrinsic::usub_with_overflow: TmpCC = X86::COND_B; break; in foldX86XALUIntrinsic()
338 Opc = X86::MOV8rm; in X86FastEmitLoad()
341 Opc = X86::MOV16rm; in X86FastEmitLoad()
344 Opc = X86::MOV32rm; in X86FastEmitLoad()
348 Opc = X86::MOV64rm; in X86FastEmitLoad()
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H A DX86InsertWait.cpp60 case X86::FNINIT: in isX87ControlInstruction()
61 case X86::FLDCW16m: in isX87ControlInstruction()
62 case X86::FNSTCW16m: in isX87ControlInstruction()
63 case X86::FNSTSW16r: in isX87ControlInstruction()
64 case X86::FNSTSWm: in isX87ControlInstruction()
65 case X86::FNCLEX: in isX87ControlInstruction()
66 case X86::FLDENVm: in isX87ControlInstruction()
67 case X86::FSTENVm: in isX87ControlInstruction()
68 case X86::FRSTORm: in isX87ControlInstruction()
69 case X86::FSAVEm: in isX87ControlInstruction()
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DX86.cpp29 case clang::X86::BI_BitScanForward: in translateX86ToMsvcIntrin()
30 case clang::X86::BI_BitScanForward64: in translateX86ToMsvcIntrin()
32 case clang::X86::BI_BitScanReverse: in translateX86ToMsvcIntrin()
33 case clang::X86::BI_BitScanReverse64: in translateX86ToMsvcIntrin()
35 case clang::X86::BI_InterlockedAnd64: in translateX86ToMsvcIntrin()
37 case clang::X86::BI_InterlockedCompareExchange128: in translateX86ToMsvcIntrin()
39 case clang::X86::BI_InterlockedExchange64: in translateX86ToMsvcIntrin()
41 case clang::X86::BI_InterlockedExchangeAdd64: in translateX86ToMsvcIntrin()
43 case clang::X86::BI_InterlockedExchangeSub64: in translateX86ToMsvcIntrin()
45 case clang::X86::BI_InterlockedOr64: in translateX86ToMsvcIntrin()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp177 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
179 return &X86::GR8RegClass; in getRegClass()
181 return &X86::GR16RegClass; in getRegClass()
183 return &X86::GR32RegClass; in getRegClass()
185 return &X86::GR64RegClass; in getRegClass()
187 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
189 return STI.hasAVX512() ? &X86::FR16XRegClass : &X86::FR16RegClass; in getRegClass()
191 return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass; in getRegClass()
193 return STI.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass; in getRegClass()
195 return STI.hasAVX512() ? &X86::VR128XRegClass : &X86::VR128RegClass; in getRegClass()
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