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/freebsd/crypto/openssh/regress/unittests/sshkey/testdata/
H A Ddsa_1.pub1 …S600VGwdPAQC/p3f0uGyrLVql0cFn1zYd/JGvtabKnIYjLaYprje/NcjwI3CZFJiz4Dp3S8kLs+X5/1DMn/Tg1Y4D4yLB+6vCt…
H A Ddsa_1-cert.pub1 …S600VGwdPAQC/p3f0uGyrLVql0cFn1zYd/JGvtabKnIYjLaYprje/NcjwI3CZFJiz4Dp3S8kLs+X5/1DMn/Tg1Y4D4yLB+6vCt…
H A Ddsa_n_pw4 uGyrLVql0cFn1zYd/JGvtabKnIYjLaYprje/NcjwI3CZFJiz4Dp3S8kLs+X5/1DMn/Tg1Y
/freebsd/crypto/openssl/test/recipes/15-test_ecparam_data/noncanon/
H A Dsecp521r1-explicit.pem8 d+/nWSj+HcEnov+o3jNIs8GFakKb+X5+McLlvWYBGDkpaniaO8AEXIpftCx9G9mY
/freebsd/sys/contrib/device-tree/src/arm64/realtek/
H A Drtd1295-xnano-x5.dts12 model = "Xnano X5";
/freebsd/sys/contrib/openzfs/module/icp/algs/skein/
H A Dskein_block.c293 uint64_t X0, X1, X2, X3, X4, X5, X6, X7; in Skein_512_Process_Block() local
303 Xptr[5] = &X5; in Skein_512_Process_Block()
342 X5 = w[5] + ks[5] + ts[0]; in Skein_512_Process_Block()
368 X5 += ks[((R) + 6) % 9] + ts[((R) + 1) % 3]; \ in Skein_512_Process_Block()
383 X5 += ks[r + (R) + 5] + ts[r + (R) + 0]; \ in Skein_512_Process_Block()
467 ctx->X[5] = X5 ^ w[5]; in Skein_512_Process_Block()
/freebsd/sys/crypto/skein/
H A Dskein_block.c266 u64b_t X0,X1,X2,X3,X4,X5,X6,X7; /* local copy of vars, for speed */ in Skein_512_Process_Block() local
271 Xptr[4] = &X4; Xptr[5] = &X5; Xptr[6] = &X6; Xptr[7] = &X7; in Skein_512_Process_Block()
304 X5 = w[5] + ks[5] + ts[0]; in Skein_512_Process_Block()
329 X5 += ks[((R)+6) % 9] + ts[((R)+1) % 3]; \ in Skein_512_Process_Block()
344 X5 += ks[r+(R)+5] + ts[r+(R)+0]; \ in Skein_512_Process_Block()
423 ctx->X[5] = X5 ^ w[5]; in Skein_512_Process_Block()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td79 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
80 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
129 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
167 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
183 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
184 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
H A DPPCCallingConv.cpp34 static const MCPhysReg ELF64ArgGPRs[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, in CC_PPC64_ELF_Shadow_GPR_Regs()
H A DPPCInstr64Bit.td1541 let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in
1543 let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in
1548 let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1550 let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1558 let Defs = [X0,X4,X5,X11,LR8,CR0] in {
1576 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1609 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx93-tqma9352.dtsi276 /* PD | FSEL 3 | DSE X5 */
280 /* HYS | FSEL 3 | X5 */
H A Dimx8mp-tqma8mpql-mba8mp-ras314.dts360 /* X5 + X6 Camera & Display interface */
H A Dimx93-tqma9352-mba93xxca.dts876 /* PD | FSEL_3 | DSE X5 */
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td92 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
164 def GPRX5 : GPRRegisterClass<(add X5)>;
172 // Don't use X1 or X5 for JALR since that is a hint to pop the return address
198 def GPRX1X5 : GPRRegisterClass<(add X1, X5)>;
H A DRISCVInstrInfo.cpp2842 // First we need to filter out candidates where the X5 register (IE t0) can't in getOutliningCandidateInfo()
2846 return !C.isAvailableAcrossAndOutOfSeq(RISCV::X5, *TRI); in getOutliningCandidateInfo()
2899 // Don't allow modifying the X5 register which we use for return addresses for in getOutliningTypeImpl()
2901 if (MI.modifiesRegister(RISCV::X5, TRI) || in getOutliningTypeImpl()
2902 MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5)) in getOutliningTypeImpl()
2938 MBB.addLiveIn(RISCV::X5); in buildOutlinedFrame()
2943 .addReg(RISCV::X5) in insertOutlinedCall()
2953 BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5) in isAddImmediate()
H A DRISCVFrameLowering.cpp1504 BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5) in spillCalleeSavedRegisters()
1657 return !RS.isRegUsed(RISCV::X5); in canUseAsPrologue()
H A DRISCVExpandPseudoInsts.cpp609 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5) in expandLoadTLSDescAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td95 [X0, X1, X3, X5]>>>,
100 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
146 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
385 CCIfSplit<CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6]>>>,
389 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
531 X0, X1, X2, X3, X4, X5,
H A DAArch64CallingConvention.cpp24 AArch64::X3, AArch64::X4, AArch64::X5,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h37 case AArch64::X5: return AArch64::W5; in getWRegFromXReg()
77 case AArch64::W5: return AArch64::X5; in getXRegFromWReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp306 return Reg == RISCV::X1 || Reg == RISCV::X5; in maybeReturnAddress()
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8916-longcheer-l8910.dts14 model = "BQ Aquaris X5 (Longcheer L8910)";
/freebsd/contrib/file/tests/
H A DHWP97.hwp.testfile34 *Bj�G�X5��r��:�ʴ�F�˄�ǹq�Ǻ��Z���U���XG��^�̀ kT-2�)���0ߗV���ܚ4ϩK9O��:�.U� R�}ؑ�i:'@�l��)��0…
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp88 if (Reg != RISCV::X1 && Reg != RISCV::X5) in DecodeGPRX1X5RegisterClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp112 {codeview::RegisterId::ARM64_X5, AArch64::X5}, in initLLVMToCVRegMapping()

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