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/freebsd/crypto/openssl/crypto/seed/
H A Dseed_local.h57 # define KEYSCHEDULE_UPDATE0(T0, T1, X1, X2, X3, X4, KC) \ argument
59 (X3) = (((X3)<<8) ^ ((X4)>>24)) & 0xffffffff; \
60 (X4) = (((X4)<<8) ^ ((T0)>>24)) & 0xffffffff; \
62 (T1) = ((X2) + (KC) - (X4)) & 0xffffffff
64 # define KEYSCHEDULE_UPDATE1(T0, T1, X1, X2, X3, X4, KC) \ argument
69 (T1) = ((X2) + (KC) - (X4)) & 0xffffffff
99 # define E_SEED(T0, T1, X1, X2, X3, X4, rbase) \ argument
101 (T1) = (X4) ^ (ks->data)[(rbase)+1]; \
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx93-tqma9352-mba93xxla.dts585 /* FSEL_2 | DSE X4 */
587 /* PD | FSEL_2 | DSE X4 */
598 /* PD | FSEL_2 | DSE X4 */
600 /* SION | HYS | FSEL_2 | DSE X4 */
610 /* PD | FSEL_2 | DSE X4 */
630 /* PD | FSEL_2 | DSE X4 */
632 /* SION | HYS | FSEL_2 | DSE X4 */
642 /* PD | FSEL_2 | DSE X4 */
664 /* PU | FSEL_3 | DSE X4 */
673 /* PU | FSEL_3 | DSE X4 */
[all …]
H A Dimx93-tqma9352-mba93xxca.dts628 /* PD | FSEL_2 | DSE X4 */
630 /* SION | HYS | FSEL_2 | DSE X4 */
640 /* PD | FSEL_2 | DSE X4 */
660 /* PD | FSEL_2 | DSE X4 */
662 /* SION | HYS | FSEL_2 | DSE X4 */
672 /* PD | FSEL_2 | DSE X4 */
694 /* PU | FSEL_3 | DSE X4 */
703 /* PU | FSEL_3 | DSE X4 */
710 /* HYS | PD | FSEL_2 | DSE X4 */
732 /* SION | HYS | OD | FSEL_3 | DSE X4 */
[all …]
H A Dimx93-tqma9352.dtsi253 /* SION | OD | FSEL 3 | DSE X4 */
282 /* HYS | FSEL 3 | X4 */
296 /* PU | FSEL 1 | DSE X4 */
/freebsd/sys/contrib/openzfs/module/icp/algs/skein/
H A Dskein_block.c293 uint64_t X0, X1, X2, X3, X4, X5, X6, X7; in Skein_512_Process_Block() local
302 Xptr[4] = &X4; in Skein_512_Process_Block()
341 X4 = w[4] + ks[4]; in Skein_512_Process_Block()
367 X4 += ks[((R) + 5) % 9]; \ in Skein_512_Process_Block()
382 X4 += ks[r + (R) + 4]; \ in Skein_512_Process_Block()
466 ctx->X[4] = X4 ^ w[4]; in Skein_512_Process_Block()
/freebsd/sys/crypto/skein/
H A Dskein_block.c266 u64b_t X0,X1,X2,X3,X4,X5,X6,X7; /* local copy of vars, for speed */ in Skein_512_Process_Block() local
271 Xptr[4] = &X4; Xptr[5] = &X5; Xptr[6] = &X6; Xptr[7] = &X7; in Skein_512_Process_Block()
303 X4 = w[4] + ks[4]; in Skein_512_Process_Block()
328 X4 += ks[((R)+5) % 9]; \ in Skein_512_Process_Block()
343 X4 += ks[r+(R)+4]; \ in Skein_512_Process_Block()
422 ctx->X[4] = X4 ^ w[4]; in Skein_512_Process_Block()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td79 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
80 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
129 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
167 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
183 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
184 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
H A DPPCCallingConv.cpp34 static const MCPhysReg ELF64ArgGPRs[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, in CC_PPC64_ELF_Shadow_GPR_Regs()
H A DPPCTLSDynamicCall.cpp97 Register GPR4 = Is64Bit ? PPC::X4 : PPC::R4; in processBlock()
H A DPPCInstr64Bit.td1541 let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in
1543 let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in
1548 let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1550 let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1553 // On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the
1558 let Defs = [X0,X4,X5,X11,LR8,CR0] in {
1576 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1609 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
H A DPPCRegisterInfo.cpp1744 SRegHi = SReg = is64Bit ? PPC::X4 : PPC::R4; in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td94 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],
100 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
146 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
222 CCIfInReg<CCIfType<[i64], CCAssignToReg<[X4]>>>,
231 // The 'nest' parameter, if any, is passed in R10 (X4).
232 CCIfNest<CCAssignToReg<[X4]>>,
385 CCIfSplit<CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6]>>>,
389 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
531 X0, X1, X2, X3, X4, X5,
H A DAArch64CallingConvention.cpp24 AArch64::X3, AArch64::X4, AArch64::X5,
H A DAArch64Processors.td244 "Cortex-X4 ARM processors", [
824 list<SubtargetFeature> X4 = [HasV9_2aOps,
1123 def : ProcessorModel<"cortex-x4", NeoverseN2Model, ProcessorFeatures.X4,
/freebsd/sys/crypto/aesni/
H A Daesni_ghash.c162 __m128i X1, __m128i X2, __m128i X3, __m128i X4, __m128i *res) in reduce4() argument
174 H4_X4_lo = _mm_clmulepi64_si128(H4, X4, 0x00); in reduce4()
183 H4_X4_hi = _mm_clmulepi64_si128(H4, X4, 0x11); in reduce4()
202 tmp7 = _mm_shuffle_epi32(X4, 78); in reduce4()
204 tmp7 = _mm_xor_si128(tmp7, X4); in reduce4()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h36 case AArch64::X4: return AArch64::W4; in getWRegFromXReg()
76 case AArch64::W4: return AArch64::X4; in getXRegFromWReg()
114 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4; in getXRegFromXRegTuple()
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr8a7742-iwg21d-q7.dts312 * ON = PCIe X4 (connector-J7)
/freebsd/contrib/ntp/scripts/stats/
H A DREADME.timecodes129 xx = 94 (unknown) (firmware revision X4.01.999 only)
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td91 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
174 // X3, and X4 as it reduces the number of register classes that get synthesized
H A DRISCVExpandPseudoInsts.cpp616 .addReg(RISCV::X4); in expandLoadTLSDescAddress()
H A DRISCVRegisterInfo.cpp120 markSuperRegs(Reserved, RISCV::X4); // tp in getReservedRegs()
H A DRISCVInstrInfoC.td711 def : InstAlias<"c.ntl.s1", (C_ADD_HINT X0, X4)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp193 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 && in expandAddTPRel()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp1080 CASE_VSHUF(32X4, r) in EmitAnyX86InstComments()
1085 CASE_VSHUF(32X4, m) in EmitAnyX86InstComments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp111 {codeview::RegisterId::ARM64_X4, AArch64::X4}, in initLLVMToCVRegMapping()

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