Searched refs:WorkingRegisters (Results 1 – 1 of 1) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PreLegalizerCombiner.cpp | 462 SmallVector<Register, 1> WorkingRegisters; in applyExtUaddvToUaddlv() local
482 extractParts(SrcReg, SrcTy, MainTy, LeftoverTy, WorkingRegisters, in applyExtUaddvToUaddlv()
485 WorkingRegisters.push_back(LeftoverRegs[I]); in applyExtUaddvToUaddlv()
488 WorkingRegisters.push_back(SrcReg); in applyExtUaddvToUaddlv()
495 for (unsigned I = 0; I < WorkingRegisters.size(); I++) { in applyExtUaddvToUaddlv()
498 LLT WorkingRegTy = MRI.getType(WorkingRegisters[I]); in applyExtUaddvToUaddlv()
501 WorkingRegisters[I] = in applyExtUaddvToUaddlv()
504 {LLT::fixed_vector(4, 16)}, {WorkingRegisters[I]}) in applyExtUaddvToUaddlv()
513 B.buildInstr(Opc, {addlvTy}, {WorkingRegisters[I]}).getReg(0); in applyExtUaddvToUaddlv()
521 WorkingRegisters[I] = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, in applyExtUaddvToUaddlv()
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