Searched refs:WideReg (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PreLegalizerCombiner.cpp | 90 Register WideReg; in matchICmpRedundantTrunc() local
92 if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) || in matchICmpRedundantTrunc()
96 LLT WideTy = MRI.getType(WideReg); in matchICmpRedundantTrunc()
97 if (KB->computeNumSignBits(WideReg) <= in matchICmpRedundantTrunc()
101 MatchInfo = WideReg; in matchICmpRedundantTrunc()
107 GISelChangeObserver &Observer, Register &WideReg) { in applyICmpRedundantTrunc() argument
110 LLT WideTy = MRI.getType(WideReg); in applyICmpRedundantTrunc()
116 MI.getOperand(2).setReg(WideReg); in applyICmpRedundantTrunc()
710 Register WideReg; in tryToSimplifyUADDO() local
711 if (mi_match(U.getParent(), MRI, m_GZExt(m_Reg(WideReg)))) { in tryToSimplifyUADDO()
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| H A D | AArch64CallLowering.cpp | 689 Register WideReg = MRI.createGenericVirtualRegister(LLT::scalar(8)); in lowerFormalArguments() local
690 OrigArg.Regs[0] = WideReg; in lowerFormalArguments()
691 BoolArgs.push_back({OrigReg, WideReg}); in lowerFormalArguments()
719 Register WideReg = KV.second; in lowerFormalArguments() local
720 LLT WideTy = MRI.getType(WideReg); in lowerFormalArguments()
724 OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1).getReg(0)); in lowerFormalArguments()
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| H A D | AArch64InstructionSelector.cpp | 5926 Register WideReg = Vec.getReg(0); in selectVectorLoadLaneIntrinsic() local
5930 !emitNarrowVector(I.getOperand(Idx).getReg(), WideReg, MIB, MRI)) in selectVectorLoadLaneIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 395 Register WideReg; in doSingleStoreMerge() local
415 WideReg = Builder.buildConstant(WideValueTy, WideConst).getReg(0); in doSingleStoreMerge()
417 Builder.buildStore(WideReg, FirstStore->getPointerReg(), *WideMMO); in doSingleStoreMerge()
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