Searched refs:VecRegSize (Results 1 – 4 of 4) sorted by relevance
1355 unsigned VecRegSize = TTI.getLoadStoreVecRegBitWidth(AS); in collectEquivalenceClasses() local1357 unsigned VF = VecRegSize / TySize; in collectEquivalenceClasses()1366 if (TySize > VecRegSize / 2 || in collectEquivalenceClasses()
2182 TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock); in Select() local2185 .isKnownMultipleOf(Subtarget->expandVScale(VecRegSize)); in Select()
10148 TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock); in lowerINSERT_SUBVECTOR() 10153 .isKnownMultipleOf(Subtarget.expandVScale(VecRegSize)); in lowerINSERT_SUBVECTOR() 10146 TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock); lowerINSERT_SUBVECTOR() local
10648 unsigned VecRegSize; in emitX86DeclareSimdFunction() member10685 Out << llvm::APSInt::getUnsigned(Data.VecRegSize / NumElts); in emitX86DeclareSimdFunction()10855 char ISA, unsigned VecRegSize, llvm::Function *Fn, SourceLocation SLoc) { in emitAArch64DeclareSimdFunction() argument