Searched refs:VecRegSize (Results 1 – 5 of 5) sorted by relevance
1483 unsigned VecRegSize = TTI.getLoadStoreVecRegBitWidth(AS); in collectEquivalenceClasses() local1485 unsigned VF = VecRegSize / TySize; in collectEquivalenceClasses()1494 if (TySize > VecRegSize / 2 || in collectEquivalenceClasses()
1204 TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock); in legalizeInsertSubvector() local1209 .isKnownMultipleOf(STI.expandVScale(VecRegSize)); in legalizeInsertSubvector()
2532 TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock); in Select() local2535 .isKnownMultipleOf(Subtarget->expandVScale(VecRegSize)); in Select()
11523 TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock); in lowerINSERT_SUBVECTOR() local11528 .isKnownMultipleOf(Subtarget.expandVScale(VecRegSize)); in lowerINSERT_SUBVECTOR()
10716 unsigned VecRegSize; in emitX86DeclareSimdFunction() member10753 Out << llvm::APSInt::getUnsigned(Data.VecRegSize / NumElts); in emitX86DeclareSimdFunction()10922 char ISA, unsigned VecRegSize, llvm::Function *Fn, SourceLocation SLoc) { in emitAArch64DeclareSimdFunction() argument