| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 694 bool HexagonMCInstrInfo::IsVecRegPair(MCRegister VecReg) { in IsVecRegPair() argument
695 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) || in IsVecRegPair()
696 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsVecRegPair()
699 bool HexagonMCInstrInfo::IsReverseVecRegPair(MCRegister VecReg) { in IsReverseVecRegPair() argument
700 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsReverseVecRegPair()
703 bool HexagonMCInstrInfo::IsVecRegSingle(MCRegister VecReg) { in IsVecRegSingle() argument
704 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31); in IsVecRegSingle()
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| H A D | HexagonMCInstrInfo.h | 366 bool IsVecRegSingle(MCRegister VecReg);
367 bool IsVecRegPair(MCRegister VecReg);
368 bool IsReverseVecRegPair(MCRegister VecReg);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVBuiltins.cpp | 1257 Register VecReg; in generateGroupInst() local
1270 VecReg = MRI->createGenericVirtualRegister( in generateGroupInst()
1272 MRI->setRegClass(VecReg, &SPIRV::vIDRegClass); in generateGroupInst()
1275 GR->assignSPIRVTypeToVReg(VecType, VecReg, MIRBuilder.getMF()); in generateGroupInst()
1277 MIRBuilder.buildInstr(TargetOpcode::G_BUILD_VECTOR).addDef(VecReg); in generateGroupInst()
1282 insertAssignInstr(VecReg, nullptr, VecType, GR, MIRBuilder, in generateGroupInst()
1297 if (VecReg.isValid()) in generateGroupInst()
1298 MIB.addUse(VecReg); in generateGroupInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2355 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2358 assert(VecReg == MI.getOperand(1).getReg()); in expandPostRAPseudo()
2362 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2364 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
2365 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)); in expandPostRAPseudo()
2387 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2400 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2402 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
2403 .addReg(VecReg, in expandPostRAPseudo()
2432 Register VecReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
[all …]
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| H A D | AMDGPURegisterBankInfo.cpp | 1954 Register VecReg = MI.getOperand(1).getReg(); in foldExtractEltToCmpSelect() local
1962 LLT VecTy = MRI.getType(VecReg); in foldExtractEltToCmpSelect()
1997 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldExtractEltToCmpSelect()
2052 Register VecReg = MI.getOperand(1).getReg(); in foldInsertEltToCmpSelect() local
2060 LLT VecTy = MRI.getType(VecReg); in foldInsertEltToCmpSelect()
2100 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldInsertEltToCmpSelect()
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| H A D | AMDGPUInstructionSelector.cpp | 3309 Register VecReg = MI.getOperand(1).getReg(); in selectG_INSERT_VECTOR_ELT() local
3318 const RegisterBank *VecRB = RBI.getRegBank(VecReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
3334 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
3360 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
3370 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
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| H A D | SIISelLowering.cpp | 4826 const TargetRegisterClass *SuperRC, unsigned VecReg, in computeIndirectRegAndOffset() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 322 Register VecReg, unsigned LaneIdx,
4020 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
4037 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI); in emitExtractVectorElt()
4038 const LLT &VecTy = MRI.getType(VecReg); in emitExtractVectorElt()
4047 Register InsertReg = VecReg; in emitExtractVectorElt()
4053 .addReg(VecReg, 0, ExtractSubReg); in emitExtractVectorElt()
4063 VecTy.getSizeInBits(), &AArch64::FPR128RegClass, VecReg, MIRBuilder); in emitExtractVectorElt()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3217 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
3218 LLT VecTy = MRI.getType(VecReg); in widenScalar()
3253 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
3254 LLT VecTy = MRI.getType(VecReg); in widenScalar()
3433 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
3434 LLT VecTy = MRI.getType(VecReg); in widenScalar()
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