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Searched refs:VecReg (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp694 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) { in IsVecRegPair() argument
695 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) || in IsVecRegPair()
696 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsVecRegPair()
699 bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) { in IsReverseVecRegPair() argument
700 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsReverseVecRegPair()
703 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) { in IsVecRegSingle() argument
704 return (VecReg > in IsVecRegSingle()
[all...]
H A DHexagonMCInstrInfo.h366 bool IsVecRegSingle(unsigned VecReg);
367 bool IsVecRegPair(unsigned VecReg);
368 bool IsReverseVecRegPair(unsigned VecReg);
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp2349 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2352 assert(VecReg == MI.getOperand(1).getReg()); in expandPostRAPseudo()
2356 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2358 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
2359 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)); in expandPostRAPseudo()
2381 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2394 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2396 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
2397 .addReg(VecReg, in expandPostRAPseudo()
2426 Register VecReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
[all …]
H A DAMDGPURegisterBankInfo.cpp1926 Register VecReg = MI.getOperand(1).getReg(); in foldExtractEltToCmpSelect() local
1934 LLT VecTy = MRI.getType(VecReg); in foldExtractEltToCmpSelect()
1969 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldExtractEltToCmpSelect()
2024 Register VecReg = MI.getOperand(1).getReg(); in foldInsertEltToCmpSelect() local
2032 LLT VecTy = MRI.getType(VecReg); in foldInsertEltToCmpSelect()
2072 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldInsertEltToCmpSelect()
H A DAMDGPUInstructionSelector.cpp3115 Register VecReg = MI.getOperand(1).getReg(); in selectG_INSERT_VECTOR_ELT() local
3124 const RegisterBank *VecRB = RBI.getRegBank(VecReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
3140 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
3166 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
3176 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
H A DSIISelLowering.cpp4603 unsigned VecReg, in computeIndirectRegAndOffset() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp322 Register VecReg, unsigned LaneIdx,
3885 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
3902 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI); in emitExtractVectorElt()
3903 const LLT &VecTy = MRI.getType(VecReg); in emitExtractVectorElt()
3912 Register InsertReg = VecReg; in emitExtractVectorElt()
3918 .addReg(VecReg, 0, ExtractSubReg); in emitExtractVectorElt()
3928 VecTy.getSizeInBits(), &AArch64::FPR128RegClass, VecReg, MIRBuilder); in emitExtractVectorElt()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2844 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2845 LLT VecTy = MRI.getType(VecReg); in widenScalar()
2880 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2881 LLT VecTy = MRI.getType(VecReg); in widenScalar()
3048 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
3049 LLT VecTy = MRI.getType(VecReg); in widenScalar()