Searched refs:VecIns (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 1143 auto *VecIns = dyn_cast<IntrinsicInst>(DupQLane->getArgOperand(0)); in instCombineSVECmpNE() local
1144 if (!VecIns || VecIns->getIntrinsicID() != Intrinsic::vector_insert) in instCombineSVECmpNE()
1149 if (!isa<UndefValue>(VecIns->getArgOperand(0))) in instCombineSVECmpNE()
1152 if (!cast<ConstantInt>(VecIns->getArgOperand(2))->isZero()) in instCombineSVECmpNE()
1155 auto *ConstVec = dyn_cast<Constant>(VecIns->getArgOperand(1)); in instCombineSVECmpNE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22479 SmallVector<SDValue, 8> VecIns; in MatchVectorAllEqualTest() local
22480 if (Op.getOpcode() == LogicOp && matchScalarReduction(Op, LogicOp, VecIns)) { in MatchVectorAllEqualTest()
22481 EVT VT = VecIns[0].getValueType(); in MatchVectorAllEqualTest()
22482 assert(llvm::all_of(VecIns, in MatchVectorAllEqualTest()
22492 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; in MatchVectorAllEqualTest()
22496 SDValue LHS = VecIns[Slot]; in MatchVectorAllEqualTest()
22497 SDValue RHS = VecIns[Slot + 1]; in MatchVectorAllEqualTest()
22498 VecIns.push_back(DAG.getNode(LogicOp, DL, VT, LHS, RHS)); in MatchVectorAllEqualTest()
22501 return LowerVectorAllEqual(DL, VecIns.back(), in MatchVectorAllEqualTest()
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