Searched refs:Vec64 (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 352 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) { in SITargetLowering()
353 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote); in SITargetLowering()
354 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
356 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
357 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
359 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
360 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
362 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
363 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
366 for (MVT Vec64 : { MVT::v3i64, MVT::v3f64 }) { in SITargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 394 SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
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| H A D | HexagonISelLowering.cpp | 2869 HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl, in contractPredicate() argument
2871 assert(ty(Vec64).getSizeInBits() == 64); in contractPredicate()
2872 if (isUndef(Vec64)) in contractPredicate()
2875 SDValue A = DAG.getBitcast(MVT::v8i8, Vec64); in contractPredicate()
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| H A D | HexagonISelLoweringHVX.cpp | 1353 SDValue Vec64 = getCombine(W1, W0, dl, MVT::v8i8, DAG); in extractHvxSubvectorPred()
1355 {Vec64, DAG.getTargetConstant(0, dl, MVT::i32)}, DAG); in extractHvxSubvectorPred()
1354 SDValue Vec64 = getCombine(W1, W0, dl, MVT::v8i8, DAG); extractHvxSubvectorPred() local
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