| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 159 MVT PartVT, EVT ValueVT, const Value *V,
170 unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
177 PartVT, ValueVT, CC)) in getCopyFromParts()
180 if (ValueVT.isVector()) in getCopyFromParts()
181 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
189 if (ValueVT.isInteger()) { in getCopyFromParts()
191 unsigned ValueBits = ValueVT.getSizeInBits(); in getCopyFromParts()
197 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
239 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
244 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in getCopyFromParts()
[all …]
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| H A D | LegalizeTypesGeneric.cpp | 254 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
255 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
279 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
463 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
464 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
475 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
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| H A D | FunctionLoweringInfo.cpp | 387 for (EVT ValueVT : ValueVTs) { in CreateRegs() local
388 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
390 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
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| H A D | LegalizeVectorTypes.cpp | 6996 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE()
6998 ValueVT.getVectorElementType(), in WidenVecOp_MSTORE()
6992 EVT ValueVT = StVal.getValueType(); WidenVecOp_MSTORE() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 81 for (EVT ValueVT : ValueVTs) in getLocalForStackObject() local
82 FuncInfo->addLocal(ValueVT.getSimpleVT()); in getLocalForStackObject()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 158 EVT ValueVT = LD->getValueType(0); in INITIALIZE_PASS() local
159 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in INITIALIZE_PASS()
163 ValueVT = MVT::i32; in INITIALIZE_PASS()
167 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in INITIALIZE_PASS()
179 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in INITIALIZE_PASS()
481 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
528 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 6338 MVT ValueVT = Node->getSimpleValueType(0); in Select() local
6344 if (!ValueVT.isVector() || !MaskVT.isVector()) in Select()
6347 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
6348 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
6381 assert(EVT(MaskVT) == EVT(ValueVT).changeVectorElementTypeToInteger() && in Select()
6412 SDVTList VTs = CurDAG->getVTList(ValueVT, MaskVT, MVT::Other); in Select()
6435 MVT ValueVT = Value.getSimpleValueType(); in Select() local
6440 if (!ValueVT.isVector()) in Select()
6443 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
6444 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 596 unsigned NumParts, MVT PartVT, EVT ValueVT,
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| H A D | SystemZISelLowering.cpp | 1580 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
1581 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
1592 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1593 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in joinRegisterPartsIntoValue()
1596 return DAG.getBitcast(ValueVT, Res); in joinRegisterPartsIntoValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 916 unsigned NumParts, MVT PartVT, EVT ValueVT,
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| H A D | ARMISelLowering.cpp | 4464 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
4465 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4466 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
4479 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4480 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4481 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
4487 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 792 unsigned NumParts, MVT PartVT, EVT ValueVT,
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| H A D | RISCVISelLowering.cpp | 21482 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts()
21483 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in splitValueIntoRegisterParts()
21496 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
21498 EVT ValueEltVT = ValueVT.getVectorElementType(); in splitValueIntoRegisterParts()
21500 unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinValue(); in splitValueIntoRegisterParts()
21535 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue()
21537 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in joinRegisterPartsIntoValue()
21544 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Va in joinRegisterPartsIntoValue()
21479 EVT ValueVT = Val.getValueType(); splitValueIntoRegisterParts() local
21532 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
[all...] |
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4479 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 22868 EVT ValueVT = Value.getValueType(); in combineI8TruncStore() local
22872 ValueVT != EVT::getVectorVT(*DAG.getContext(), MVT::i8, 3)) in combineI8TruncStore()
22919 EVT ValueVT = Value.getValueType(); in performSTORECombine() local
22936 ValueVT.isFixedLengthVector() && in performSTORECombine()
22937 ValueVT.getFixedSizeInBits() >= Subtarget->getMinSVEVectorSizeInBits() && in performSTORECombine()
22957 if (!isHalvingTruncateOfLegalScalableType(ValueVT, StoreVT)) in performSTORECombine()
23011 EVT ValueVT = Value->getValueType(0); in performMSTORECombine() local
23013 if (!isHalvingTruncateOfLegalScalableType(ValueVT, MemVT)) in performMSTORECombine()
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