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Searched refs:ValueVT (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp155 MVT PartVT, EVT ValueVT, const Value *V,
166 unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
173 PartVT, ValueVT, CC)) in getCopyFromParts()
176 if (ValueVT.isVector()) in getCopyFromParts()
177 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
185 if (ValueVT.isInteger()) { in getCopyFromParts()
187 unsigned ValueBits = ValueVT.getSizeInBits(); in getCopyFromParts()
193 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
235 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
240 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in getCopyFromParts()
[all …]
H A DLegalizeTypesGeneric.cpp254 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
255 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
278 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
482 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
483 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
494 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
H A DFunctionLoweringInfo.cpp392 for (EVT ValueVT : ValueVTs) { in CreateRegs() local
393 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
395 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
H A DLegalizeVectorTypes.cpp7455 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE() local
7456 WideVT = EVT::getVectorVT(*DAG.getContext(), ValueVT.getVectorElementType(), in WidenVecOp_MSTORE()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp79 for (EVT ValueVT : ValueVTs) in getLocalForStackObject() local
80 FuncInfo->addLocal(ValueVT.getSimpleVT()); in getLocalForStackObject()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp158 EVT ValueVT = LD->getValueType(0); in INITIALIZE_PASS() local
159 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in INITIALIZE_PASS()
163 ValueVT = MVT::i32; in INITIALIZE_PASS()
167 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in INITIALIZE_PASS()
179 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in INITIALIZE_PASS()
482 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
529 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h422 MVT PartVT, EVT ValueVT,
H A DLoongArchISelLowering.cpp8483 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
8485 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in splitValueIntoRegisterParts()
8503 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
8506 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in joinRegisterPartsIntoValue()
8513 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp6495 MVT ValueVT = Node->getSimpleValueType(0); in Select() local
6501 if (!ValueVT.isVector() || !MaskVT.isVector()) in Select()
6504 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
6505 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
6538 assert(EVT(MaskVT) == EVT(ValueVT).changeVectorElementTypeToInteger() && in Select()
6569 SDVTList VTs = CurDAG->getVTList(ValueVT, MaskVT, MVT::Other); in Select()
6592 MVT ValueVT = Value.getSimpleValueType(); in Select() local
6597 if (!ValueVT.isVector()) in Select()
6600 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
6601 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h615 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DSystemZISelLowering.cpp1908 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
1909 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
1920 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1921 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in joinRegisterPartsIntoValue()
1924 return DAG.getBitcast(ValueVT, Res); in joinRegisterPartsIntoValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h344 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DRISCVISelLowering.cpp23923 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
23926 if ((ValueVT == PairVT || in splitValueIntoRegisterParts()
23928 ValueVT == MVT::f64)) && in splitValueIntoRegisterParts()
23932 if (ValueVT == MVT::f64) in splitValueIntoRegisterParts()
23941 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in splitValueIntoRegisterParts()
23954 if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) { in splitValueIntoRegisterParts()
23956 unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields(); in splitValueIntoRegisterParts()
23958 divideCeil(ValueVT.getSizeInBits().getKnownMinValue(), in splitValueIntoRegisterParts()
23975 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
23977 EVT ValueEltVT = ValueVT.getVectorElementType(); in splitValueIntoRegisterParts()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h942 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DARMISelLowering.cpp4534 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
4535 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4536 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
4549 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4550 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4551 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
4557 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp23921 EVT ValueVT = Value.getValueType(); in combineI8TruncStore() local
23925 ValueVT != EVT::getVectorVT(*DAG.getContext(), MVT::i8, 3)) in combineI8TruncStore()
23988 EVT ValueVT = Value.getValueType(); in performSTORECombine() local
24021 ValueVT.isFixedLengthVector() && in performSTORECombine()
24022 ValueVT.getFixedSizeInBits() >= Subtarget->getMinSVEVectorSizeInBits() && in performSTORECombine()
24041 isHalvingTruncateOfLegalScalableType(ValueVT, MemVT)) { in performSTORECombine()
24059 if (!ValueVT.isInteger()) in performSTORECombine()
24064 SDValue ZeroElt = DAG.getConstant(0, DL, ValueVT); in performSTORECombine()
24069 if (ValueVT != MemVT && !ST->isTruncatingStore()) in performSTORECombine()
24165 EVT ValueVT = Value->getValueType(0); in performMSTORECombine() local
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4654 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument