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Searched refs:ValueTypeByHwMode (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DInfoByHwMode.cpp31 ValueTypeByHwMode::ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH) { in ValueTypeByHwMode() function in ValueTypeByHwMode
42 ValueTypeByHwMode::ValueTypeByHwMode(Record *R, MVT T) : ValueTypeByHwMode(T) { in ValueTypeByHwMode() function in ValueTypeByHwMode
47 bool ValueTypeByHwMode::operator==(const ValueTypeByHwMode &T) const { in operator ==()
58 bool ValueTypeByHwMode::operator<(const ValueTypeByHwMode &T) const { in operator <()
64 MVT &ValueTypeByHwMode::getOrCreateTypeForMode(unsigned Mode, MVT Type) { in getOrCreateTypeForMode()
77 StringRef ValueTypeByHwMode::getMVTName(MVT T) { in getMVTName()
83 void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const { in writeToStream()
103 void ValueTypeByHwMode::dump() const { dbgs() << *this << '\n'; } in dump()
105 ValueTypeByHwMode llvm::getValueTypeByHwMode(Record *Rec, in getValueTypeByHwMode()
114 return ValueTypeByHwMode(Rec, CGH); in getValueTypeByHwMode()
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H A DInfoByHwMode.h154 struct ValueTypeByHwMode : public InfoByHwMode<MVT> { struct
155 ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH);
156 ValueTypeByHwMode(Record *R, MVT T);
157 ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode, T}); } in ValueTypeByHwMode() function
158 ValueTypeByHwMode() = default;
160 bool operator==(const ValueTypeByHwMode &T) const;
161 bool operator<(const ValueTypeByHwMode &T) const;
177 ValueTypeByHwMode getValueTypeByHwMode(Record *Rec, const CodeGenHwModes &CGH); argument
179 raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T);
H A DCodeGenTarget.h65 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
127 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
145 std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
147 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const { in getLegalValueTypes()
H A DCodeGenDAGPatterns.h195 : TypeSetByHwMode(ValueTypeByHwMode(VT)) {} in TypeSetByHwMode()
196 TypeSetByHwMode(ValueTypeByHwMode VT) in TypeSetByHwMode()
197 : TypeSetByHwMode(ArrayRef<ValueTypeByHwMode>(&VT, 1)) {} in TypeSetByHwMode()
198 TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList);
203 ValueTypeByHwMode getValueTypeByHwMode() const;
225 bool insert(const ValueTypeByHwMode &VVT);
253 ValueTypeByHwMode getConcrete(const TypeSetByHwMode &VTS, in getConcrete()
267 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) const { in MergeInTypeInfo()
300 const ValueTypeByHwMode &VVT);
403 ValueTypeByHwMode VVT;
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H A DCodeGenTarget.cpp180 const ValueTypeByHwMode &ValueTy, CodeGenRegBank &RegBank, in getSuperRegForSubReg()
241 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) const { in getRegisterVTs()
243 std::vector<ValueTypeByHwMode> Result; in getRegisterVTs()
246 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); in getRegisterVTs()
H A DCodeGenRegisters.h350 SmallVector<ValueTypeByHwMode, 4> VTs;
378 ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; } in getValueTypes()
380 bool hasType(const ValueTypeByHwMode &VT) const;
382 const ValueTypeByHwMode &getValueTypeNum(unsigned VTNum) const { in getValueTypeNum()
793 getMinimalPhysRegClass(Record *RegRecord, ValueTypeByHwMode *VT = nullptr);
H A DCodeGenDAGPatterns.cpp66 OS << LS << ValueTypeByHwMode::getMVTName(T); in writeToStream()
76 TypeSetByHwMode::TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList) { in TypeSetByHwMode()
81 for (const ValueTypeByHwMode &VVT : VTList) in TypeSetByHwMode()
95 ValueTypeByHwMode TypeSetByHwMode::getValueTypeByHwMode() const { in getValueTypeByHwMode()
98 ValueTypeByHwMode VVT; in getValueTypeByHwMode()
115 bool TypeSetByHwMode::insert(const ValueTypeByHwMode &VVT) { in insert()
640 const ValueTypeByHwMode &VVT) { in EnforceVectorEltTypeIs()
2474 ValueTypeByHwMode VVT = TP.getInfer().getConcrete(Types[0], false); in ApplyTypeConstraints()
2706 const ValueTypeByHwMode VVT = getValueTypeByHwMode(T, CGH); in ApplyTypeConstraints()
H A DCodeGenInstruction.cpp526 const std::vector<ValueTypeByHwMode> &RegVTs = in HasOneImplicitDefWithKnownVT()
H A DCodeGenRegisters.cpp888 bool CodeGenRegisterClass::hasType(const ValueTypeByHwMode &VT) const { in hasType()
900 for (const ValueTypeByHwMode &OurVT : VTs) { in hasType()
2497 ValueTypeByHwMode *VT) { in getMinimalPhysRegClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td474 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
476 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
478 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
480 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
482 def VecF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
484 def VecF32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
487 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
489 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
491 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
493 def VecPF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td124 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
127 def XLenFVT : ValueTypeByHwMode<[RV64],
129 def XLenPairFVT : ValueTypeByHwMode<[RV32],
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherGen.cpp38 const ValueTypeByHwMode &VVT = RC.getValueTypeNum(0); in getRegisterValueType()
46 const ValueTypeByHwMode &VVT = RC.getValueTypeNum(0); in getRegisterValueType()
H A DRegisterInfoEmitter.cpp1225 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1289 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
H A DFastISelEmitter.cpp189 ValueTypeByHwMode VVT = TP->getTree(0)->getType(0); in emitImmediatePredicate()
H A DGlobalISelEmitter.cpp1109 ValueTypeByHwMode VT = ChildTypes.front().getValueTypeByHwMode(); in importChildMatcher()
1147 ValueTypeByHwMode VTy = ChildTypes.front().getValueTypeByHwMode(); in importChildMatcher()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td94 def GRLenVT : ValueTypeByHwMode<[LA32, LA64],
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td55 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
66 class PtrValueTypeByHwMode<ValueTypeByHwMode scalar, int addrspace>