| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 49 unsigned ValueReg, unsigned Address,
55 unsigned ValueReg, unsigned Address,
245 unsigned ValueReg, unsigned Address,
253 unsigned ValueReg, unsigned Address,
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| H A D | R600InstrInfo.cpp | 1087 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1089 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1094 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1110 AddrReg, ValueReg) in buildIndirectWrite()
1119 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1121 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectRead()
1126 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1142 ValueReg, in buildIndirectRead()
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| H A D | SIRegisterInfo.cpp | 1216 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
1230 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1231 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1234 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()
1331 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1349 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
1543 ? ValueReg in buildSpillLoadStore()
1544 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1577 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1578 : ValueReg; in buildSpillLoadStore()
[all …]
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| H A D | SIRegisterInfo.h | 428 unsigned LoadStoreOp, int Index, Register ValueReg,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVBuiltins.cpp | 332 Register ValueReg = BitcastMI->getOperand(2).getReg(); in getBlockStructInstr() local
333 MachineInstr *ValueMI = MRI->getUniqueVRegDef(ValueReg); in getBlockStructInstr()
359 Register ValueReg = MI->getOperand(0).getReg(); in getMachineInstrType() local
362 NextMI->getOperand(1).getReg() != ValueReg) in getMachineInstrType()
808 Register ValueReg = Call->Arguments[1]; in buildAtomicRMWInst() local
819 MRI->createGenericVirtualRegister(MRI->getType(ValueReg)); in buildAtomicRMWInst()
825 .addUse(ValueReg); in buildAtomicRMWInst()
828 ValueReg = NegValueReg; in buildAtomicRMWInst()
837 .addUse(ValueReg); in buildAtomicRMWInst()
860 Register ValueReg = Call->Arguments[3]; in buildAtomicFloatingRMWInst() local
[all …]
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| H A D | SPIRVInstructionSelector.cpp | 908 Register ValueReg = I.getOperand(2).getReg(); in selectAtomicRMW() local
912 Result |= selectUnOpWithSrc(TmpReg, ResType, I, ValueReg, NegateOpcode); in selectAtomicRMW()
913 ValueReg = TmpReg; in selectAtomicRMW()
922 .addUse(ValueReg) in selectAtomicRMW()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 1295 Register ValueReg = getRegForValue(Store->getValueOperand()); in selectStore() local
1296 if (ValueReg == 0) in selectStore()
1299 ValueReg = maskI1Value(ValueReg, Store->getValueOperand()); in selectStore()
1305 MIB.addReg(ValueReg); in selectStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode() local
185 const LLT Ty = MRI.getType(ValueReg); in selectLoadStoreOpCode()
192 if (isRegInGprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
222 if (isRegInFprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12225 Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitPartwordAtomicBinary() local
12226 BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg) in EmitPartwordAtomicBinary()
12228 MI.getOperand(3).setReg(ValueReg); in EmitPartwordAtomicBinary()
12229 incr = ValueReg; in EmitPartwordAtomicBinary()
12372 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary() local
12375 ValueReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12376 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg) in EmitPartwordAtomicBinary()
12381 .addReg(ValueReg); in EmitPartwordAtomicBinary()
12382 ValueReg = ValueSReg; in EmitPartwordAtomicBinary()
12385 BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ValueReg).addReg(CmpReg); in EmitPartwordAtomicBinary()
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