| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AttributeImpl.h | 194 unsigned ValSize; variable
196 return KindSize + 1 + ValSize + 1; in numTrailingObjects()
202 ValSize(Val.size()) { in AttributeImpl()
208 TrailingString[KindSize + 1 + ValSize] = '\0'; in AttributeImpl()
215 return StringRef(getTrailingObjects<char>() + KindSize + 1, ValSize); in getStringValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 297 uint64_t ValSize = VA.getValVT().getFixedSizeInBits(); in assignValueToReg() local
300 assert(ValSize <= 64 && "Unsupported value size"); in assignValueToReg()
304 if (ValSize == LocSize) { in assignValueToReg()
307 assert(ValSize < LocSize && "Extensions not supported"); in assignValueToReg()
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| H A D | ARMInstructionSelector.cpp | 1101 const auto ValSize = ValTy.getSizeInBits(); in select() local
1103 assert((ValSize != 64 || STI.hasVFP2Base()) && in select()
1106 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 723 unsigned ValSize = StoredValTy.getSizeInBits(); in optimizeConsecutiveMemOpAddressing() local
724 if (ValSize < 32 || St->getMMO().getSizeInBits() != ValSize) in optimizeConsecutiveMemOpAddressing()
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| H A D | AArch64LegalizerInfo.cpp | 1851 uint64_t ValSize = ValTy.getSizeInBits() / 8; in legalizeVaArg() local
1857 auto Size = MIRBuilder.buildConstant(IntPtrTy, alignTo(ValSize, PtrAlign)); in legalizeVaArg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 3122 unsigned ValSize = ValTy.getSizeInBits(); in selectG_INSERT_VECTOR_ELT() local
3146 if (VecRB->getID() == AMDGPU::VGPRRegBankID && ValSize != 32) in selectG_INSERT_VECTOR_ELT()
3151 computeIndirectRegIndex(*MRI, TRI, VecRC, IdxReg, ValSize / 8, *KB); in selectG_INSERT_VECTOR_ELT()
3164 VecSize, ValSize, VecRB->getID() == AMDGPU::SGPRRegBankID); in selectG_INSERT_VECTOR_ELT()
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| H A D | SIISelLowering.cpp | 6116 unsigned ValSize = VT.getSizeInBits(); in lowerLaneOp() local
6121 MVT IntVT = MVT::getIntegerVT(ValSize); in lowerLaneOp()
6169 if (ValSize == 32) { in lowerLaneOp()
6174 if (ValSize < 32) { in lowerLaneOp()
6194 if (ValSize % 32 != 0) in lowerLaneOp()
6251 for (unsigned i = 0, EltIdx = 0; i < ValSize / 32; i++) { in lowerLaneOp()
6277 MVT VecVT = MVT::getVectorVT(MVT::i32, ValSize / 32); in lowerLaneOp()
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| H A D | AMDGPULegalizerInfo.cpp | 3097 const unsigned ValSize = ValTy.getSizeInBits(); in legalizeLoad() local
3109 if (WideMemSize == ValSize) { in legalizeLoad()
3121 if (ValSize > WideMemSize) in legalizeLoad()
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| H A D | AMDGPUISelLowering.cpp | 6022 unsigned ValSize = DL.getTypeSizeInBits(RMW->getType()); in shouldExpandAtomicRMWInIR() local
6023 if (ValSize == 32 || ValSize == 64) in shouldExpandAtomicRMWInIR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 684 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments_64() local
689 Offset += 8 - ValSize; in LowerFormalArguments_64()
690 int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true); in LowerFormalArguments_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 515 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments() local
530 int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true); in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7238 const unsigned ValSize = ValVT.getStoreSize(); in LowerFormalArguments_AIX() local
7239 assert((ValSize <= LocSize) && in LowerFormalArguments_AIX()
7243 if (LocSize > ValSize) in LowerFormalArguments_AIX()
7244 CurArgOffset += LocSize - ValSize; in LowerFormalArguments_AIX()
7249 int FI = MFI.CreateFixedObject(ValSize, CurArgOffset, IsImmutable); in LowerFormalArguments_AIX()
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