| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AttributeImpl.h | 197 unsigned ValSize; variable
202 ValSize(Val.size()) { in AttributeImpl()
208 TrailingString[KindSize + 1 + ValSize] = '\0'; in AttributeImpl()
215 return StringRef(getTrailingObjects() + KindSize + 1, ValSize); in getStringValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 297 uint64_t ValSize = VA.getValVT().getFixedSizeInBits(); in assignValueToReg() local
300 assert(ValSize <= 64 && "Unsupported value size"); in assignValueToReg()
304 if (ValSize == LocSize) { in assignValueToReg()
307 assert(ValSize < LocSize && "Extensions not supported"); in assignValueToReg()
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| H A D | ARMInstructionSelector.cpp | 1101 const auto ValSize = ValTy.getSizeInBits(); in select() local
1103 assert((ValSize != 64 || STI.hasVFP2Base()) && in select()
1126 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 839 unsigned ValSize = StoredValTy.getSizeInBits(); in optimizeConsecutiveMemOpAddressing() local
840 if (ValSize < 32 || St->getMMO().getSizeInBits() != ValSize) in optimizeConsecutiveMemOpAddressing()
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| H A D | AArch64LegalizerInfo.cpp | 1992 uint64_t ValSize = ValTy.getSizeInBits() / 8; in legalizeVaArg() local
1998 auto Size = MIRBuilder.buildConstant(IntPtrTy, alignTo(ValSize, PtrAlign)); in legalizeVaArg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 2196 unsigned ValSize = DL.getTypeSizeInBits(RMW->getType()); in shouldExpandAtomicRMWInIR() local
2197 if (ValSize == 32 || ValSize == 64) in shouldExpandAtomicRMWInIR()
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| H A D | AMDGPUInstructionSelector.cpp | 3316 unsigned ValSize = ValTy.getSizeInBits(); in selectG_INSERT_VECTOR_ELT() local
3340 if (VecRB->getID() == AMDGPU::VGPRRegBankID && ValSize != 32) in selectG_INSERT_VECTOR_ELT()
3345 computeIndirectRegIndex(*MRI, TRI, VecRC, IdxReg, ValSize / 8, *VT); in selectG_INSERT_VECTOR_ELT()
3358 VecSize, ValSize, VecRB->getID() == AMDGPU::SGPRRegBankID); in selectG_INSERT_VECTOR_ELT()
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| H A D | SIISelLowering.cpp | 6460 unsigned ValSize = VT.getSizeInBits(); in lowerLaneOp() local
6467 MVT IntVT = MVT::getIntegerVT(ValSize); in lowerLaneOp()
6470 if (IID == Intrinsic::amdgcn_update_dpp && (ValSize % 64 == 0) && in lowerLaneOp()
6527 if (ValSize == SplitSize) { in lowerLaneOp()
6532 if (ValSize < 32) { in lowerLaneOp()
6552 if (ValSize % SplitSize != 0) in lowerLaneOp()
6613 for (unsigned i = 0, EltIdx = 0; i < ValSize / SplitSize; i++) { in lowerLaneOp()
6641 MVT::getVectorVT(MVT::getIntegerVT(SplitSize), ValSize / SplitSize); in lowerLaneOp()
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| H A D | AMDGPULegalizerInfo.cpp | 3155 const unsigned ValSize = ValTy.getSizeInBits(); in legalizeLoad() local
3167 if (WideMemSize == ValSize) { in legalizeLoad()
3179 if (ValSize > WideMemSize) in legalizeLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 688 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments_64() local
693 Offset += 8 - ValSize; in LowerFormalArguments_64()
694 int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true); in LowerFormalArguments_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 513 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments() local
528 int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true); in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7276 const unsigned ValSize = ValVT.getStoreSize(); in LowerFormalArguments_AIX() local
7277 assert((ValSize <= LocSize) && in LowerFormalArguments_AIX()
7281 if (LocSize > ValSize) in LowerFormalArguments_AIX()
7282 CurArgOffset += LocSize - ValSize; in LowerFormalArguments_AIX()
7287 int FI = MFI.CreateFixedObject(ValSize, CurArgOffset, IsImmutable); in LowerFormalArguments_AIX()
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