Searched refs:ValOp (Results 1 – 10 of 10) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInlineAsmLowering.cpp | 27 Value *ValOp = nullptr; in lowerAsmOperandForConstraint() local
29 ValOp = Val; in lowerAsmOperandForConstraint()
36 ValOp = II->getOperand(0); in lowerAsmOperandForConstraint()
43 return ValOp ? InlineAsmLowering::lowerAsmOperandForConstraint( in lowerAsmOperandForConstraint()
44 ValOp, Constraint, Ops, MIRBuilder) in lowerAsmOperandForConstraint()
|
| H A D | SPIRVEmitIntrinsics.cpp | 885 Value *ValOp = CI->getArgOperand(3); in deduceOperandElementTypeCalledFunction() local
886 KnownElemTy = isPointerTy(ValOp->getType()) in deduceOperandElementTypeCalledFunction()
888 : ValOp->getType(); in deduceOperandElementTypeCalledFunction()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2695 const MachineOperand &ValOp = MI.getOperand(TakeOp); in evaluateHexCondMove() local
2699 if (ValOp.isImm()) { in evaluateHexCondMove()
2700 int64_t V = ValOp.getImm(); in evaluateHexCondMove()
2708 if (ValOp.isReg()) { in evaluateHexCondMove()
2709 RegSubRegPair R(getRegSubRegPair(ValOp)); in evaluateHexCondMove()
|
| H A D | HexagonSplitDouble.cpp | 631 MachineOperand &ValOp = Load ? MI->getOperand(0) in splitMemRef() local
634 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
|
| H A D | HexagonBitSimplify.cpp | 1932 MachineOperand &ValOp = MI->getOperand(2); in genStoreUpperHalf() local
1933 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf()
1944 ValOp.setReg(H.Reg); in genStoreUpperHalf()
1945 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | SROA.cpp | 1136 Value *ValOp = SI.getValueOperand(); in visitStoreInst() local
1137 if (ValOp == *U) in visitStoreInst()
1142 TypeSize StoreSize = DL.getTypeStoreSize(ValOp->getType()); in visitStoreInst()
1169 assert((!SI.isSimple() || ValOp->getType()->isSingleValueType()) && in visitStoreInst()
1171 handleLoadOrStore(ValOp->getType(), SI, Offset, Size, SI.isVolatile()); in visitStoreInst()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AtomicExpandPass.cpp | 992 Value *ValOp = Builder.CreateBitCast(AI->getValOperand(), PMV.IntValueType); in expandPartwordAtomicRMW() local
994 Builder.CreateShl(Builder.CreateZExt(ValOp, PMV.WordType), PMV.ShiftAmt, in expandPartwordAtomicRMW()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 8152 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorStores() local
8157 EVT ValVT = ValOp.getValueType(); in GenWidenVectorStores()
8201 SDValue EOp = DAG.getExtractSubvector(dl, NewVT, ValOp, Idx); in GenWidenVectorStores()
8214 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); in GenWidenVectorStores()
|
| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 5225 const MDOperand &ValOp = (*OpIt)->getOperand(2); in UpgradeDebugInfo() local
5226 if (auto *CI = mdconst::dyn_extract_or_null<ConstantInt>(ValOp)) in UpgradeDebugInfo()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 8547 SDValue ValOp = N->getOperand(0); in combineFCOPYSIGN() local
8553 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, ValOp, WideOp); in combineFCOPYSIGN()
|