Searched refs:ValOp (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInlineAsmLowering.cpp | 27 Value *ValOp = nullptr; in lowerAsmOperandForConstraint() local
29 ValOp = Val; in lowerAsmOperandForConstraint()
36 ValOp = II->getOperand(0); in lowerAsmOperandForConstraint()
43 return ValOp ? InlineAsmLowering::lowerAsmOperandForConstraint( in lowerAsmOperandForConstraint()
44 ValOp, Constraint, Ops, MIRBuilder) in lowerAsmOperandForConstraint()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | InferAlignment.cpp | 38 Value *ValOp = SI->getValueOperand(); in tryToImproveAlign() local
40 Align NewAlign = Fn(PtrOp, OldAlign, DL.getPrefTypeAlign(ValOp->getType())); in tryToImproveAlign()
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| H A D | SROA.cpp | 1124 Value *ValOp = SI.getValueOperand(); in visitStoreInst() local
1125 if (ValOp == *U) in visitStoreInst()
1130 TypeSize StoreSize = DL.getTypeStoreSize(ValOp->getType()); in visitStoreInst()
1152 assert((!SI.isSimple() || ValOp->getType()->isSingleValueType()) && in visitStoreInst()
1154 handleLoadOrStore(ValOp->getType(), SI, Offset, Size, SI.isVolatile()); in visitStoreInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2691 const MachineOperand &ValOp = MI.getOperand(TakeOp); in evaluateHexCondMove() local
2695 if (ValOp.isImm()) { in evaluateHexCondMove()
2696 int64_t V = ValOp.getImm(); in evaluateHexCondMove()
2704 if (ValOp.isReg()) { in evaluateHexCondMove()
2705 RegisterSubReg R(ValOp); in evaluateHexCondMove()
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| H A D | HexagonSplitDouble.cpp | 637 MachineOperand &ValOp = Load ? MI->getOperand(0) in splitMemRef() local
640 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
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| H A D | HexagonBitSimplify.cpp | 1954 MachineOperand &ValOp = MI->getOperand(2); in genStoreUpperHalf() local
1955 BitTracker::RegisterRef RS = ValOp; in genStoreUpperHalf()
1966 ValOp.setReg(H.Reg); in genStoreUpperHalf()
1967 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AtomicExpandPass.cpp | 913 Value *ValOp = Builder.CreateBitCast(AI->getValOperand(), PMV.IntValueType); in expandPartwordAtomicRMW() local
915 Builder.CreateShl(Builder.CreateZExt(ValOp, PMV.WordType), PMV.ShiftAmt, in expandPartwordAtomicRMW()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 7633 SDValue ValOp = GetWidenedVector(ST->getValue()); in GenWidenVectorStores()
7638 EVT ValVT = ValOp.getValueType(); in GenWidenVectorStores()
7682 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, in GenWidenVectorStores()
7696 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); in GenWidenVectorStores()
7629 SDValue ValOp = GetWidenedVector(ST->getValue()); GenWidenVectorStores() local
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