Searched refs:VZIP (Results 1 – 7 of 7) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 207 VZIP, // zip (interleave) enumerator
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H A D | ARMScheduleR52.td | 830 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
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H A D | ARMScheduleSwift.td | 600 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
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H A D | ARMISelLowering.cpp | 1797 MAKE_CASE(ARMISD::VZIP) in getTargetNodeName() 7565 return ARMISD::VZIP; in isNEONTwoResultShuffleMask() 7573 return ARMISD::VZIP; in isNEONTwoResultShuffleMask() 8526 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
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H A D | ARMISelDAGToDAG.cpp | 4267 case ARMISD::VZIP: { in Select()
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H A D | ARMInstrNEON.td | 525 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>; 2620 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. 7161 // VZIP : Vector Zip (Interleave)
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
H A D | arm_neon.td | 668 def VZIP : WInst<"vzip", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
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