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Searched refs:VX (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepIICHVX.td238 InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/
275 InstrItinData <tc_3c8c15d0, /*SLOT23,VX*/
308 InstrItinData <tc_4942646a, /*SLOT23,VX*/
364 InstrItinData <tc_5cdf8c84, /*SLOT23,VX*/
374 InstrItinData <tc_649072c2, /*SLOT23,VX*/
524 InstrItinData <tc_a19b9305, /*SLOT23,VX*/
559 InstrItinData <tc_ac4046bc, /*SLOT23,VX*/
569 InstrItinData <tc_b091f1c6, /*SLOT23,VX*/
600 InstrItinData <tc_c127de3a, /*SLOT23,VX*/
605 InstrItinData <tc_c4edf264, /*SLOT23,VX*/
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp3799 case CASE_VMA_OPCODE_LMULS(MADD, VX): in findCommutedOpIndices()
3800 case CASE_VMA_OPCODE_LMULS(NMSUB, VX): in findCommutedOpIndices()
3801 case CASE_VMA_OPCODE_LMULS(MACC, VX): in findCommutedOpIndices()
3802 case CASE_VMA_OPCODE_LMULS(NMSAC, VX): in findCommutedOpIndices()
3982 case CASE_VMA_OPCODE_LMULS(MADD, VX): in commuteInstructionImpl()
3983 case CASE_VMA_OPCODE_LMULS(NMSUB, VX): in commuteInstructionImpl()
3984 case CASE_VMA_OPCODE_LMULS(MACC, VX): in commuteInstructionImpl()
3985 case CASE_VMA_OPCODE_LMULS(NMSAC, VX): in commuteInstructionImpl()
4008 CASE_VMA_CHANGE_OPCODE_LMULS(MACC, MADD, VX) in commuteInstructionImpl()
4009 CASE_VMA_CHANGE_OPCODE_LMULS(MADD, MACC, VX) in commuteInstructionImpl()
[all …]
H A DRISCVInstrInfoVSDPatterns.td134 def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
312 : VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VX",
H A DRISCVInstrInfoVVLPatterns.td951 def : VPatBinaryVL_XI<vop, instruction_name, "VX",
982 def : VPatBinaryVL_XI<vop, instruction_name, "VX",
H A DRISCVInstrInfoVPseudos.td5332 defm : VPatBinaryMaskOut<intrinsic, instruction, "VX",
5585 defm : VPatTernaryWithPolicy<intrinsic, instruction, "VX",
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td2051 // E-2 VX-Form
2103 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
2117 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
2146 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
2164 /// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
2197 // VX-Form: [PO VRT EO VRB 1 PS XO]
2216 // VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
H A DPPCInstrP10.td22 // (X-Form, VX-Form, etc.)
161 // VX-Form: [ PO VT R VB RC XO ]
381 // VX-Form: [PO VRT RA VRB XO].
388 // VX-Form: [PO VRT RA RB XO].
395 // VX-Form: [ PO BF // VRA VRB XO ]
H A DPPCInstrAltivec.td487 // VX-Form instructions. AltiVec arithmetic ops.
1441 // VX-Form: [PO VRT / UIM VRB XO].
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DASTContext.cpp14173 const auto *VX = cast<VectorType>(X), *VY = cast<VectorType>(Y); in getCommonNonSugarTypeNode() local
14174 assert(VX->getNumElements() == VY->getNumElements()); in getCommonNonSugarTypeNode()
14175 assert(VX->getVectorKind() == VY->getVectorKind()); in getCommonNonSugarTypeNode()
14176 return Ctx.getVectorType(getCommonElementType(Ctx, VX, VY), in getCommonNonSugarTypeNode()
14177 VX->getNumElements(), VX->getVectorKind()); in getCommonNonSugarTypeNode()
14180 const auto *VX = cast<ExtVectorType>(X), *VY = cast<ExtVectorType>(Y); in getCommonNonSugarTypeNode() local
14181 assert(VX->getNumElements() == VY->getNumElements()); in getCommonNonSugarTypeNode()
14182 return Ctx.getExtVectorType(getCommonElementType(Ctx, VX, VY), in getCommonNonSugarTypeNode()
14183 VX->getNumElements()); in getCommonNonSugarTypeNode()
14186 const auto *VX = cast<DependentSizedExtVectorType>(X), in getCommonNonSugarTypeNode() local
[all …]
/freebsd/sys/dev/acpica/
H A Dacpi_quirks287 # Hitachi Flora 270VX-NH7
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DAPInt.cpp2984 APInt VX = (A*X + B)*X + C; in SolveQuadraticEquationWrap() local
2985 APInt VY = VX + TwoA*X + A + B; in SolveQuadraticEquationWrap()
2987 VX.isNegative() != VY.isNegative() || VX.isZero() != VY.isZero(); in SolveQuadraticEquationWrap()
/freebsd/contrib/file/magic/Magdir/
H A Dgames668 # RGSSAD asset archive used in RPG Maker XP, VX and VX Ace
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td19 // MicroOp Count/Types: #(B|X|Y|Z|LD|ST|SD|VX|VY|VSD)
23 // down one Z pipe, six SD pipes, four VX pipes and the total latency is
H A DAArch64ISelLowering.cpp7116 SDValue VX = in LowerFLDEXP() local
7125 VPg, VX, VExp); in LowerFLDEXP()
/freebsd/crypto/openssl/crypto/perlasm/
H A Ds390x.pm42 VX => [qw(vgef vgeg vgbm vzero vone vgm vgmb vgmh vgmf vgmg
/freebsd/share/misc/
H A Dusb_vendors2379 00f4 LifeCam VX-6000 (SN9C20x + OV9650)
2380 00f5 LifeCam VX-3000
2382 00f7 LifeCam VX-1000
2562 0723 LifeCam VX-7000 (UVC-compliant)
2564 0728 LifeCam VX-5000
2570 074a LifeCam VX-500 [1357]
2574 0761 LifeCam VX-2000
2576 0766 LifeCam VX-800
2580 0770 LifeCam VX-700
15673 001b Real Aracde Pro.VX
[all …]
H A Dpci_vendors11394 061b G92GL [Quadro VX 200]
30216 883d 86c988 [ViRGE/VX]
38378 7030 430VX - 82437VX TVX [Triton VX]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrVector.td645 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>;
1055 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>;
H A DSystemZScheduleZ13.td1253 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;
H A DSystemZScheduleZ17.td1336 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;
H A DSystemZScheduleZ15.td1311 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;
H A DSystemZScheduleZ14.td1274 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;
H A DSystemZScheduleZ16.td1317 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp29398 SDValue VX = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorType, X); in LowerFMINIMUM_FMAXIMUM() local
29404 SDValue IsNanZero = DAG.getNode(X86ISD::VFPCLASSS, DL, MVT::v1i1, VX, Imm); in LowerFMINIMUM_FMAXIMUM()
29423 SDValue VX = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, Ins); in LowerFMINIMUM_FMAXIMUM() local
29424 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VX, in LowerFMINIMUM_FMAXIMUM()