Searched refs:VWMUL_VL (Results 1 – 3 of 3) sorted by relevance
324 VWMUL_VL, enumerator
6105 if (Opcode >= RISCVISD::VWMUL_VL && Opcode <= RISCVISD::VFWSUB_W_VL) in hasMergeOp() 14402 return RISCVISD::VWMUL_VL; in getSExtOpcode() 16305 case RISCVISD::VWMUL_VL: in combineToVWMACC() 16341 unsigned Opc = RISCVISD::VWMACC_VL + MulOp.getOpcode() - RISCVISD::VWMUL_VL; in combineToVWMACC() 16346 static_assert(RISCVISD::VWMUL_VL + 1 == RISCVISD::VWMULU_VL, in combineToVWMACC() 16347 "Unexpected opcode after VWMUL_VL!"); in combineToVWMACC() 16348 static_assert(RISCVISD::VWMUL_VL + 2 == RISCVISD::VWMULSU_VL, in combineToVWMACC() 16349 "Unexpected opcode after VWMUL_VL!"); in combineToVWMACC() 20563 NODE_NAME_CASE(VWMUL_VL) in getTargetNodeName()
427 def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWIntBinOp_VL, [SDNPCommutative]>;