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Searched refs:VWADDU_W_VL (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h332 VWADDU_W_VL, enumerator
H A DRISCVISelLowering.cpp4840 Interleaved = DAG.getNode(RISCVISD::VWADDU_W_VL, DL, WideContainerVT, in getWideningInterleave()
14392 case RISCVISD::VWADDU_W_VL: in getSExtOpcode()
14415 case RISCVISD::VWADDU_W_VL: in getZExtOpcode()
14467 : RISCVISD::VWADDU_W_VL; in getWOpcode()
14623 case RISCVISD::VWADDU_W_VL: in isSupportedRoot()
14661 case RISCVISD::VWADDU_W_VL: in NodeExtensionHelper()
14668 Opc == RISCVISD::VWADDU_W_VL || Opc == RISCVISD::VWSUBU_W_VL; in NodeExtensionHelper()
14715 case RISCVISD::VWADDU_W_VL: in isCommutative()
14953 case RISCVISD::VWADDU_W_VL: in getSupportedFoldings()
15083 assert(Opc == RISCVISD::VWADD_W_VL || Opc == RISCVISD::VWADDU_W_VL || in combineVWADDSUBWSelect()
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H A DRISCVInstrInfoVVLPatterns.td483 def riscv_vwaddu_w_vl : SDNode<"RISCVISD::VWADDU_W_VL", SDT_RISCVVWIntBinOpW_VL>;