Searched refs:VVT (Results 1 – 10 of 10) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenDAGPatterns.cpp | 82 for (const ValueTypeByHwMode &VVT : VTList) in TypeSetByHwMode() local
83 insert(VVT); in TypeSetByHwMode()
99 ValueTypeByHwMode VVT; in getValueTypeByHwMode() local
100 VVT.PtrAddrSpace = AddrSpace; in getValueTypeByHwMode()
104 VVT.getOrCreateTypeForMode(I.first, T); in getValueTypeByHwMode()
106 return VVT; in getValueTypeByHwMode()
116 bool TypeSetByHwMode::insert(const ValueTypeByHwMode &VVT) { in insert() argument
121 for (const auto &P : VVT) { in insert()
136 if (!VVT.hasMode(I.first)) in insert()
639 const ValueTypeByHwMode &VVT) { in EnforceVectorEltTypeIs() argument
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| H A D | CodeGenDAGPatterns.h | 223 bool insert(const ValueTypeByHwMode &VVT);
299 const ValueTypeByHwMode &VVT);
381 ValueTypeByHwMode VVT; member
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | DAGISelMatcherGen.cpp | 38 const ValueTypeByHwMode &VVT = RC.getValueTypeNum(0); in getRegisterValueType() local
39 assert(VVT.isSimple()); in getRegisterValueType()
40 VT = VVT.getSimple().SimpleTy; in getRegisterValueType()
46 const ValueTypeByHwMode &VVT = RC.getValueTypeNum(0); in getRegisterValueType() local
47 assert(VVT.isSimple() && VVT.getSimple().SimpleTy == VT && in getRegisterValueType()
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| H A D | RegisterInfoEmitter.cpp | 1264 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc() local
1265 if (VVT.hasDefault() || VVT.hasMode(M)) in runTargetDesc()
1266 S.push_back(VVT.get(M).SimpleTy); in runTargetDesc()
1328 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc() local
1329 if (VVT.hasDefault() || VVT.hasMode(M)) in runTargetDesc()
1330 VTs.push_back(VVT.get(M).SimpleTy); in runTargetDesc()
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| H A D | SDNodeInfoEmitter.cpp | 208 if (C.VVT.isSimple()) in emitTypeConstraint()
209 VT = C.VVT.getSimple(); in emitTypeConstraint()
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| H A D | FastISelEmitter.cpp | 182 ValueTypeByHwMode VVT = TP->getTree(0)->getType(0); in emitImmediatePredicate() local
183 assert(VVT.isSimple() && in emitImmediatePredicate()
185 OS << LS << "VT == " << getEnumName(VVT.getSimple().SimpleTy) << " && "; in emitImmediatePredicate()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 2182 llvm::VectorType *VVT = dyn_cast<llvm::VectorType>(Init->getType()); in VisitInitListExpr() local
2187 if (!VVT) { in VisitInitListExpr()
2230 unsigned InitElts = cast<llvm::FixedVectorType>(VVT)->getNumElements(); in VisitInitListExpr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2052 EVT VVT = SubOp.getNode()->getValueType(0); in LowerCONCAT_VECTORS() local
2053 EVT EltVT = VVT.getVectorElementType(); in LowerCONCAT_VECTORS()
2054 unsigned NumSubElem = VVT.getVectorNumElements(); in LowerCONCAT_VECTORS()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 18858 SDValue VVT = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, V); in PerformMVEExtCombine() local
18860 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, VVT, in PerformMVEExtCombine()
18862 : DAG.getZeroExtendInReg(VVT, DL, ExtVT); in PerformMVEExtCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7744 MVT VVT = MVT::getVectorVT(VT.getScalarType(), NumElm); in lowerBuildVectorAsBroadcast() local
7751 Ops, VVT, MPI, Alignment, in lowerBuildVectorAsBroadcast()
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