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Searched refs:VVT (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherGen.cpp38 const ValueTypeByHwMode &VVT = RC.getValueTypeNum(0); in getRegisterValueType() local
39 assert(VVT.isSimple()); in getRegisterValueType()
40 VT = VVT.getSimple().SimpleTy; in getRegisterValueType()
46 const ValueTypeByHwMode &VVT = RC.getValueTypeNum(0); in getRegisterValueType() local
47 assert(VVT.isSimple() && VVT.getSimple().SimpleTy == VT && in getRegisterValueType()
H A DRegisterInfoEmitter.cpp1225 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc() local
1226 if (VVT.hasDefault() || VVT.hasMode(M)) in runTargetDesc()
1227 S.push_back(VVT.get(M).SimpleTy); in runTargetDesc()
1289 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc() local
1290 if (VVT.hasDefault() || VVT.hasMode(M)) in runTargetDesc()
1291 VTs.push_back(VVT.get(M).SimpleTy); in runTargetDesc()
H A DFastISelEmitter.cpp189 ValueTypeByHwMode VVT = TP->getTree(0)->getType(0); in emitImmediatePredicate() local
190 assert(VVT.isSimple() && in emitImmediatePredicate()
192 OS << "VT == " << getEnumName(VVT.getSimple().SimpleTy) << " && "; in emitImmediatePredicate()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenDAGPatterns.cpp81 for (const ValueTypeByHwMode &VVT : VTList) in TypeSetByHwMode() local
82 insert(VVT); in TypeSetByHwMode()
98 ValueTypeByHwMode VVT; in getValueTypeByHwMode() local
99 VVT.PtrAddrSpace = AddrSpace; in getValueTypeByHwMode()
103 VVT.getOrCreateTypeForMode(I.first, T); in getValueTypeByHwMode()
105 return VVT; in getValueTypeByHwMode()
115 bool TypeSetByHwMode::insert(const ValueTypeByHwMode &VVT) { in insert() argument
120 for (const auto &P : VVT) { in insert()
135 if (!VVT.hasMode(I.first)) in insert()
640 const ValueTypeByHwMode &VVT) { in EnforceVectorEltTypeIs() argument
[all …]
H A DCodeGenDAGPatterns.h225 bool insert(const ValueTypeByHwMode &VVT);
300 const ValueTypeByHwMode &VVT);
403 ValueTypeByHwMode VVT; member
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2264 EVT VVT = SubOp.getNode()->getValueType(0); in LowerCONCAT_VECTORS() local
2265 EVT EltVT = VVT.getVectorElementType(); in LowerCONCAT_VECTORS()
2266 unsigned NumSubElem = VVT.getVectorNumElements(); in LowerCONCAT_VECTORS()
6135 EVT VVT; in ReplaceLoadVector() local
6138 VVT = MVT::v2f16; in ReplaceLoadVector()
6141 VVT = MVT::v2bf16; in ReplaceLoadVector()
6144 VVT = MVT::v2i16; in ReplaceLoadVector()
6149 EVT ListVTs[] = {VVT, VVT, VVT, VVT, MVT::Other}; in ReplaceLoadVector()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprScalar.cpp2081 llvm::VectorType *VVT = dyn_cast<llvm::VectorType>(Init->getType()); in VisitInitListExpr() local
2086 if (!VVT) { in VisitInitListExpr()
2129 unsigned InitElts = cast<llvm::FixedVectorType>(VVT)->getNumElements(); in VisitInitListExpr()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp18787 SDValue VVT = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, V); in PerformMVEExtCombine() local
18789 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, VVT, in PerformMVEExtCombine()
18791 : DAG.getZeroExtendInReg(VVT, DL, ExtVT); in PerformMVEExtCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp7380 MVT VVT = MVT::getVectorVT(VT.getScalarType(), NumElm); in lowerBuildVectorAsBroadcast() local
7387 Ops, VVT, MPI, Alignment, in lowerBuildVectorAsBroadcast()