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Searched refs:VTSize (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp199 unsigned VTSize = 4; in EmitTargetCodeForMemcpy() local
237 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
238 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
258 VTSize = getRemainingSize(BytesLeft); in EmitTargetCodeForMemcpy()
265 SrcOff += VTSize; in EmitTargetCodeForMemcpy()
266 BytesLeft -= VTSize; in EmitTargetCodeForMemcpy()
274 VTSize = getRemainingSize(BytesLeft); in EmitTargetCodeForMemcpy()
280 DstOff += VTSize; in EmitTargetCodeForMemcpy()
281 BytesLeft -= VTSize; in EmitTargetCodeForMemcpy()
H A DARMCallLowering.cpp83 unsigned VTSize = VT.getSimpleVT().getSizeInBits(); in isSupportedType() local
85 if (VTSize == 64) in isSupportedType()
89 return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32; in isSupportedType()
H A DARMISelLowering.cpp8268 uint64_t VTSize = VT.getFixedSizeInBits(); in ReconstructShuffle() local
8269 if (SrcVTSize == VTSize) in ReconstructShuffle()
8275 unsigned NumSrcElts = VTSize / EltVT.getFixedSizeInBits(); in ReconstructShuffle()
8278 if (SrcVTSize < VTSize) { in ReconstructShuffle()
8279 if (2 * SrcVTSize != VTSize) in ReconstructShuffle()
8289 if (SrcVTSize != 2 * VTSize) in ReconstructShuffle()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1193 unsigned VTSize = VT.getScalarSizeInBits(); in earlyExpandDIVFIX() local
1202 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2); in earlyExpandDIVFIX()
1215 assert(SatW <= VTSize && in earlyExpandDIVFIX()
1217 Res = SaturateWidenedDIVFIX(Res, dl, SatW == 0 ? VTSize : SatW, Signed, in earlyExpandDIVFIX()
4247 unsigned VTSize = VT.getScalarSizeInBits(); in ExpandIntRes_MULFIX() local
4268 APInt MinVal = APInt::getSignedMinValue(VTSize); in ExpandIntRes_MULFIX()
4269 APInt MaxVal = APInt::getSignedMaxValue(VTSize); in ExpandIntRes_MULFIX()
4282 APInt MaxVal = APInt::getMaxValue(VTSize); in ExpandIntRes_MULFIX()
4293 assert(Scale <= VTSize && "Scale can't be larger than the value type size."); in ExpandIntRes_MULFIX()
4316 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half " in ExpandIntRes_MULFIX()
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H A DTargetLowering.cpp234 unsigned VTSize = VT.getSizeInBits() / 8; in findOptimalMemOpLowering() local
235 while (VTSize > Size) { in findOptimalMemOpLowering()
272 VTSize = Size; in findOptimalMemOpLowering()
275 VTSize = NewVTSize; in findOptimalMemOpLowering()
283 Size -= VTSize; in findOptimalMemOpLowering()
10649 unsigned VTSize = VT.getScalarSizeInBits(); in expandFixedPointMul() local
10663 APInt MinVal = APInt::getSignedMinValue(VTSize); in expandFixedPointMul()
10664 APInt MaxVal = APInt::getSignedMaxValue(VTSize); in expandFixedPointMul()
10679 APInt MaxVal = APInt::getMaxValue(VTSize); in expandFixedPointMul()
10685 assert(((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && in expandFixedPointMul()
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H A DSelectionDAG.cpp7886 unsigned VTSize = VT.getSizeInBits() / 8; in getMemcpyLoadsAndStores() local
7889 if (VTSize > Size) { in getMemcpyLoadsAndStores()
7893 SrcOff -= VTSize - Size; in getMemcpyLoadsAndStores()
7894 DstOff -= VTSize - Size; in getMemcpyLoadsAndStores()
7912 SubSlice.Length = VTSize; in getMemcpyLoadsAndStores()
7934 SrcPtrInfo.getWithOffset(SrcOff).isDereferenceable(VTSize, C, DL); in getMemcpyLoadsAndStores()
7954 SrcOff += VTSize; in getMemcpyLoadsAndStores()
7955 DstOff += VTSize; in getMemcpyLoadsAndStores()
7956 Size -= VTSize; in getMemcpyLoadsAndStores()
8076 unsigned VTSize = VT.getSizeInBits() / 8; in getMemmoveLoadsAndStores() local
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H A DDAGCombiner.cpp20028 TypeSize VTSize = VT.getSizeInBits(); in TransformFPLoadStorePair() local
20032 if (VTSize.isScalable()) in TransformFPLoadStorePair()
20036 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedValue()); in TransformFPLoadStorePair()
23100 uint64_t VTSize = VT.getFixedSizeInBits(); in createBuildVecShuffle() local
23110 if ((VTSize % InVT1Size == 0) && InVT1 == InVT2) { in createBuildVecShuffle()
23113 unsigned NumConcats = VTSize / InVT1Size; in createBuildVecShuffle()
23120 } else if (InVT1Size == VTSize * 2) { in createBuildVecShuffle()
23156 } else if (InVT2Size * 2 == VTSize && InVT1Size == VTSize) { in createBuildVecShuffle()
23160 } else if (InVT1Size / VTSize > 1 && InVT1Size % VTSize == 0) { in createBuildVecShuffle()
23182 ShuffleNumElems = InVT1Size / VTSize * NumElems; in createBuildVecShuffle()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4404 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorFP_TO_INT() local
4406 if (VTSize < InVTSize) { in LowerVectorFP_TO_INT()
4421 if (VTSize > InVTSize) { in LowerVectorFP_TO_INT()
4688 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorINT_TO_FP() local
4690 if (VTSize < InVTSize) { in LowerVectorINT_TO_FP()
4706 if (VTSize > InVTSize) { in LowerVectorINT_TO_FP()
11687 uint64_t VTSize = VT.getFixedSizeInBits(); in getRegForInlineAsmConstraint() local
11688 if (VTSize == 16) in getRegForInlineAsmConstraint()
11690 if (VTSize == 32) in getRegForInlineAsmConstraint()
11692 if (VTSize == 64) in getRegForInlineAsmConstraint()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp7495 uint64_t VTSize = DL->getTypeStoreSizeInBits(getWidenedType(EltTy, N)); in canMapToVector() local
7496 if (VTSize < MinVecRegSize || VTSize > MaxVecRegSize || in canMapToVector()
7497 VTSize != DL->getTypeStoreSizeInBits(T)) in canMapToVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp19186 unsigned VTSize = VT.getSizeInBits(); in lowerFPToIntToFP() local
19189 MVT VecVT = MVT::getVectorVT(VT, 128 / VTSize); in lowerFPToIntToFP()
19195 IntSize != VTSize ? X86ISD::CVTSI2P : (unsigned)ISD::SINT_TO_FP; in lowerFPToIntToFP()