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Searched refs:VT (Results 1 – 25 of 328) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp167 EVT VT = N->getValueType(0); in SelectExtractHigh() local
170 if (!VT.is64BitVector() || !LVT.is128BitVector() || in SelectExtractHigh()
171 Index != VT.getVectorNumElements()) in SelectExtractHigh()
181 EVT VT = Op.getValueType(); in SelectRoundingVLShr() local
183 if (ShtAmt > VT.getScalarSizeInBits() / 2 || Op.getOpcode() != ISD::ADD) in SelectRoundingVLShr()
188 Imm = APInt(VT.getScalarSizeInBits(), in SelectRoundingVLShr()
193 Imm = APInt(VT.getScalarSizeInBits(), in SelectRoundingVLShr()
254 template<MVT::SimpleValueType VT>
256 return SelectSVEAddSubImm(N, VT, Imm, Shift); in SelectSVEAddSubImm()
259 template <MVT::SimpleValueType VT, bool Negate>
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H A DAArch64ISelLowering.cpp172 static inline EVT getPackedSVEVectorVT(EVT VT) { in getPackedSVEVectorVT() argument
173 switch (VT.getSimpleVT().SimpleTy) { in getPackedSVEVectorVT()
212 static inline EVT getPromotedVTForPredicate(EVT VT) { in getPromotedVTForPredicate() argument
213 assert(VT.isScalableVector() && (VT.getVectorElementType() == MVT::i1) && in getPromotedVTForPredicate()
215 switch (VT.getVectorMinNumElements()) { in getPromotedVTForPredicate()
234 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType() argument
235 assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && in isPackedVectorType()
237 return VT.isFixedLengthVector() || in isPackedVectorType()
238 VT.getSizeInBits().getKnownMinValue() == AArch64::SVEBitsPerBlock; in isPackedVectorType()
453 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
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H A DAArch64FastISel.cpp185 bool isTypeLegal(Type *Ty, MVT &VT);
186 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
190 bool simplifyAddress(Address &Addr, MVT VT);
228 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
230 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
232 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
239 unsigned emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm);
268 unsigned materializeInt(const ConstantInt *CI, MVT VT);
269 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
320 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor() argument
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DVTEmitter.cpp32 static void VTtoGetLLVMTyString(raw_ostream &OS, const Record *VT) { in VTtoGetLLVMTyString() argument
33 bool IsVector = VT->getValueAsBit("isVector"); in VTtoGetLLVMTyString()
35 OS << (VT->getValueAsBit("isScalable") ? "Scalable" : "Fixed") in VTtoGetLLVMTyString()
38 auto OutputVT = IsVector ? VT->getValueAsDef("ElementType") : VT; in VTtoGetLLVMTyString()
76 OS << ", " << VT->getValueAsInt("nElem") << ")"; in VTtoGetLLVMTyString()
84 for (auto *VT : ValueTypes) { in run() local
85 auto Number = VT->getValueAsInt("Value"); in run()
89 VTsByNumber[Number] = VT; in run()
113 for (const auto *VT : VTsByNumber) { in run() local
114 if (!VT) in run()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h44 bool operator==(EVT VT) const {
45 return !(*this != VT);
47 bool operator!=(EVT VT) const {
48 if (V.SimpleTy != VT.V.SimpleTy)
51 return LLVMTy != VT.LLVMTy;
73 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements,
75 MVT M = MVT::getVectorVT(VT.V, NumElements, IsScalable);
78 return getExtendedVectorVT(Context, VT, NumElements, IsScalable);
83 static EVT getVectorVT(LLVMContext &Context, EVT VT, ElementCount EC) { in getVectorVT()
84 MVT M = MVT::getVectorVT(VT.V, EC); in getVectorVT()
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H A DTargetLowering.h458 virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const { in shouldExpandGetActiveLaneMask() argument
469 virtual bool shouldExpandCttzElements(EVT VT) const { return true; } in shouldExpandCttzElements() argument
479 virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const { in shouldReassociateReduction() argument
501 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction() argument
503 if (VT.getVectorElementCount().isScalar()) in getPreferredVectorAction()
506 if (!VT.isPow2VectorType()) in getPreferredVectorAction()
543 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap() argument
546 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem() argument
567 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
573 int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
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H A DSelectionDAG.h114 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
115 FastID(ID), VTs(VT), NumVTs(Num) {
653 SDVTList getVTList(EVT VT);
668 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
670 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
673 SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
675 return getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), DL, VT,
679 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
683 SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL);
684 SDValue getShiftAmountConstant(const APInt &Val, EVT VT, const SDLoc &DL);
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp206 EVT VT = getOptimalMemOpType(Op, FuncAttributes); in findOptimalMemOpLowering() local
208 if (VT == MVT::Other) { in findOptimalMemOpLowering()
212 VT = MVT::LAST_INTEGER_VALUETYPE; in findOptimalMemOpLowering()
214 while (Op.getDstAlign() < (VT.getSizeInBits() / 8) && in findOptimalMemOpLowering()
215 !allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign())) in findOptimalMemOpLowering()
216 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering()
217 assert(VT.isInteger()); in findOptimalMemOpLowering()
227 if (VT.bitsGT(LVT)) in findOptimalMemOpLowering()
228 VT = LVT; in findOptimalMemOpLowering()
234 unsigned VTSize = VT.getSizeInBits() / 8; in findOptimalMemOpLowering()
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H A DDAGCombiner.cpp256 for (MVT VT : MVT::all_valuetypes()) in DAGCombiner() local
257 if (EVT(VT).isSimple() && VT != MVT::Other && in DAGCombiner()
258 TLI.isTypeLegal(EVT(VT)) && in DAGCombiner()
259 VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits) in DAGCombiner()
260 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue(); in DAGCombiner()
343 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
344 APInt DemandedElts = VT.isFixedLengthVector() in SimplifyDemandedBits()
345 ? APInt::getAllOnes(VT.getVectorNumElements()) in SimplifyDemandedBits()
404 SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
580 EVT VT, SDValue N0, SDValue N1,
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H A DMatchContext.h41 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() argument
42 return TLI.isOperationLegal(Op, VT); in isOperationLegal()
45 bool isOperationLegalOrCustom(unsigned Op, EVT VT,
47 return TLI.isOperationLegalOrCustom(Op, VT, LegalOnly);
111 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { in getNode() argument
115 return DAG.getNode(VPOpcode, DL, VT, in getNode()
119 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
124 return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp}); in getNode()
127 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
132 return DAG.getNode(VPOpcode, DL, VT, in getNode()
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H A DSelectionDAG.cpp128 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType() argument
130 assert(VT.isFloatingPoint() && "Can only convert between FP types"); in isValueValidForType()
135 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT), in isValueValidForType()
1123 EVT VT = N->getValueType(0); in VerifySDNode() local
1125 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
1130 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && in VerifySDNode()
1132 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && in VerifySDNode()
1199 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1200 if (VT.isExtended()) { in RemoveNodeFromCSEMaps()
1201 Erased = ExtendedValueTypeNodes.erase(VT); in RemoveNodeFromCSEMaps()
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H A DLegalizeVectorOps.cpp709 MVT VT = Node->getSimpleValueType(0); in Promote() local
710 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); in Promote()
734 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || in Promote()
735 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
737 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, in Promote()
740 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote()
750 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType(); in PromoteINT_TO_FP() local
751 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); in PromoteINT_TO_FP()
752 assert(NVT.getVectorNumElements() == VT.getVectorNumElements() && in PromoteINT_TO_FP()
788 MVT VT = Node->getSimpleValueType(0); in PromoteFP_TO_INT() local
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h261 SimpleValueType VT = EltTyTable[SimpleTy - FIRST_VALUETYPE]; in getVectorElementType() local
262 assert(VT != INVALID_SIMPLE_VALUE_TYPE && "Not a vector MVT!"); in getVectorElementType()
263 return VT; in getVectorElementType()
371 bool knownBitsGT(MVT VT) const { in knownBitsGT() argument
372 return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits()); in knownBitsGT()
377 bool knownBitsGE(MVT VT) const { in knownBitsGE() argument
378 return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits()); in knownBitsGE()
382 bool knownBitsLT(MVT VT) const { in knownBitsLT() argument
383 return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits()); in knownBitsLT()
388 bool knownBitsLE(MVT VT) const { in knownBitsLE() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp202 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
203 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
216 for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) { in X86TargetLowering()
217 setCondCodeAction(ISD::SETOEQ, VT, Expand); in X86TargetLowering()
218 setCondCodeAction(ISD::SETUNE, VT, Expand); in X86TargetLowering()
330 for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) { in X86TargetLowering()
331 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom); in X86TargetLowering()
332 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in X86TargetLowering()
366 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) { in X86TargetLowering()
367 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
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H A DX86InterleavedAccess.cpp229 static MVT scaleVectorType(MVT VT) { in scaleVectorType() argument
230 unsigned ScalarSize = VT.getVectorElementType().getScalarSizeInBits() * 2; in scaleVectorType()
232 VT.getVectorNumElements() / 2); in scaleVectorType()
257 static void genShuffleBland(MVT VT, ArrayRef<int> Mask, in genShuffleBland() argument
260 assert(VT.getSizeInBits() >= 256 && in genShuffleBland()
262 unsigned NumOfElm = VT.getVectorNumElements(); in genShuffleBland()
287 static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix, in reorderSubVector() argument
302 genShuffleBland(VT, VPShuf, OptimizeShuf, (i / Stride) * 16, in reorderSubVector()
327 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
338 createUnpackShuffleMask(VT, MaskLowTemp1, true, false); in interleave8bitStride4VF8()
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H A DX86ISelLowering.h989 MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override { in getScalarShiftAmountTy() argument
1021 bool isSafeMemOpType(MVT VT) const override;
1023 bool isMemoryAccessFast(EVT VT, Align Alignment) const;
1027 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
1036 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1041 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1044 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), in allowsMemoryAccess()
1060 bool preferABDSToABSWithNSW(EVT VT) const override;
1062 bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT,
1066 EVT VT) const override;
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp103 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, in getFPLibCall() argument
110 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
111 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
112 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
113 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
114 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
447 MVT VT) { in getOUTLINE_ATOMIC() argument
448 if (!VT.isScalarInteger()) in getOUTLINE_ATOMIC()
450 uint64_t MemSize = VT.getScalarSizeInBits() / 8; in getOUTLINE_ATOMIC()
488 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC() argument
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H A DCallingConvLower.cpp90 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
103 MVT VT = Outs[i].VT; in CheckReturn() local
105 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
117 MVT VT = Outs[i].VT; in AnalyzeReturn() local
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in AnalyzeReturn()
130 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands()
165 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
167 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
170 << VT << '\n'; in AnalyzeCallResult()
178 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp63 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
65 VT.isInteger() ? RISCVISD::VMV_V_X_VL : RISCVISD::VFMV_V_F_VL; in PreprocessISelDAG()
69 if (VT.isInteger()) in PreprocessISelDAG()
72 Result = CurDAG->getNode(Opc, DL, VT, CurDAG->getUNDEF(VT), Src, VL); in PreprocessISelDAG()
80 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
85 assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() && in PreprocessISelDAG()
107 SDVTList VTs = CurDAG->getVTList({VT, MVT::Other}); in PreprocessISelDAG()
175 static SDValue selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, in selectImmSeq() argument
177 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT); in selectImmSeq()
179 SDValue SDImm = CurDAG->getTargetConstant(Inst.getImm(), DL, VT); in selectImmSeq()
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H A DRISCVISelLowering.cpp165 auto addRegClassForRVV = [this](MVT VT) { in RISCVTargetLowering() argument
169 if (VT.getVectorMinNumElements() < MinElts) in RISCVTargetLowering()
172 unsigned Size = VT.getSizeInBits().getKnownMinValue(); in RISCVTargetLowering()
185 addRegisterClass(VT, RC); in RISCVTargetLowering()
188 for (MVT VT : BoolVecVTs) in RISCVTargetLowering() local
189 addRegClassForRVV(VT); in RISCVTargetLowering()
190 for (MVT VT : IntVecVTs) { in RISCVTargetLowering() local
191 if (VT.getVectorElementType() == MVT::i64 && in RISCVTargetLowering()
194 addRegClassForRVV(VT); in RISCVTargetLowering()
198 for (MVT VT in RISCVTargetLowering() local
202 for (MVT VT : BF16VecVTs) RISCVTargetLowering() local
206 for (MVT VT : F32VecVTs) RISCVTargetLowering() local
210 for (MVT VT : F64VecVTs) RISCVTargetLowering() local
214 __anon765c18b70202(MVT VT) RISCVTargetLowering() argument
220 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) RISCVTargetLowering() local
224 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) RISCVTargetLowering() local
745 for (MVT VT : BoolVecVTs) { RISCVTargetLowering() local
815 for (MVT VT : IntVecVTs) { RISCVTargetLowering() local
968 __anon765c18b70302(MVT VT) RISCVTargetLowering() argument
1046 __anon765c18b70402(MVT VT, ArrayRef<MVT::SimpleValueType> SmallerVTs) RISCVTargetLowering() argument
1054 for (MVT VT : F16VecVTs) { RISCVTargetLowering() local
1060 for (MVT VT : F16VecVTs) { RISCVTargetLowering() local
1096 for (MVT VT : BF16VecVTs) { RISCVTargetLowering() local
1117 for (MVT VT : F32VecVTs) { RISCVTargetLowering() local
1126 for (MVT VT : F64VecVTs) { RISCVTargetLowering() local
1136 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { RISCVTargetLowering() local
1285 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { RISCVTargetLowering() local
1962 EVT VT = Y.getValueType(); hasAndNotCompare() local
2253 isFPImmLegal(const APFloat & Imm,EVT VT,bool ForCodeSize) const isFPImmLegal() argument
2368 getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const getVectorTypeBreakdownForCallingConv() argument
2448 getLMUL(MVT VT) getLMUL() argument
2492 getSubregIndexByMVT(MVT VT,unsigned Index) getSubregIndexByMVT() argument
2515 getRegClassIDForVecVT(MVT VT) getRegClassIDForVecVT() argument
2605 useRVVForFixedLengthVectorVT(MVT VT,const RISCVSubtarget & Subtarget) useRVVForFixedLengthVectorVT() argument
2681 getContainerForFixedLengthVector(const TargetLowering & TLI,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2716 getContainerForFixedLengthVector(SelectionDAG & DAG,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2727 convertToScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertToScalableVector() argument
2739 convertFromScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertFromScalableVector() argument
2847 shouldExpandBuildVectorWithShuffles(EVT VT,unsigned DefinedValues) const shouldExpandBuildVectorWithShuffles() argument
3041 MVT VT = Op.getSimpleValueType(); lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local
3151 MVT VT = Op.getSimpleValueType(); lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() local
3251 MVT VT = Op.getSimpleValueType(); lowerFTRUNC_FCEIL_FFLOOR_FROUND() local
3279 MVT VT = Op.getSimpleValueType(); lowerVectorXRINT() local
3303 getVSlidedown(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlidedown() argument
3315 getVSlideup(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlideup() argument
3325 getLMUL1VT(MVT VT) getLMUL1VT() argument
3470 matchSplatAsGather(SDValue SplatVal,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) matchSplatAsGather() argument
3514 MVT VT = Op.getSimpleValueType(); lowerBuildVectorViaDominantValues() local
3621 MVT VT = Op.getSimpleValueType(); lowerBuildVectorOfConstants() local
3943 MVT VT = Op.getSimpleValueType(); lowerBuildVectorViaPacking() local
4000 MVT VT = Op.getSimpleValueType(); lowerBUILD_VECTORvXf16() local
4011 MVT VT = Op.getSimpleValueType(); lowerBUILD_VECTOR() local
4237 splatPartsI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Lo,SDValue Hi,SDValue VL,SelectionDAG & DAG) splatPartsI64WithVL() argument
4293 splatSplitI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Scalar,SDValue VL,SelectionDAG & DAG) splatSplitI64WithVL() argument
4306 lowerScalarSplat(SDValue Passthru,SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarSplat() argument
4343 lowerScalarInsert(SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarInsert() argument
4403 isDeinterleaveShuffle(MVT VT,MVT ContainerVT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget) isDeinterleaveShuffle() argument
4448 isInterleaveShuffle(ArrayRef<int> Mask,MVT VT,int & EvenSrc,int & OddSrc,const RISCVSubtarget & Subtarget) isInterleaveShuffle() argument
4558 getDeinterleaveViaVNSRL(const SDLoc & DL,MVT VT,SDValue Src,bool EvenElts,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) getDeinterleaveViaVNSRL() argument
4617 lowerVECTOR_SHUFFLEAsVSlidedown(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlidedown() argument
4694 lowerVECTOR_SHUFFLEAsVSlideup(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlideup() argument
4738 lowerVECTOR_SHUFFLEAsVSlide1(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlide1() argument
4896 MVT VT = SVN->getSimpleValueType(0); lowerBitreverseShuffle() local
4950 EVT VT = SVN->getValueType(0); isLegalBitRotate() local
4972 EVT VT = SVN->getValueType(0); lowerVECTOR_SHUFFLEAsRotate() local
4999 MVT VT = SVN->getSimpleValueType(0); lowerShuffleViaVRegSplitting() local
5083 MVT VT = Op.getSimpleValueType(); lowerVECTOR_SHUFFLE() local
5404 MVT VT = Op.getSimpleValueType(); lowerCTLZ_CTTZ_ZERO_UNDEF() local
5571 MVT VT = Op.getSimpleValueType(); expandUnalignedRVVLoad() local
5602 MVT VT = StoredVal.getSimpleValueType(); expandUnalignedRVVStore() local
5760 MVT VT = Op.getSimpleValueType(); LowerIS_FPCLASS() local
5862 MVT VT = Op.getSimpleValueType(); lowerFMAXIMUM_FMINIMUM() local
6297 EVT VT = Op.getValueType(); LowerOperation() local
6379 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6414 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6435 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6491 EVT VT = Op.getValueType(); LowerOperation() local
6508 EVT VT = Op.getValueType(); LowerOperation() local
6571 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6720 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6867 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6932 EVT VT = Op.getValueType(); LowerOperation() local
6945 MVT VT = Op.getSimpleValueType(); LowerOperation() local
7047 EVT VT = Op->getValueType(0); LowerOperation() local
7562 MVT VT = N->getSimpleValueType(0); combineSelectToBinOp() local
7665 EVT VT = BO->getValueType(0); foldBinOpIntoSelectIfProfitable() local
7696 MVT VT = Op.getSimpleValueType(); lowerSELECT() local
7916 EVT VT = Op.getValueType(); lowerFRAMEADDR() local
7942 EVT VT = Op.getValueType(); lowerRETURNADDR() local
7966 EVT VT = Lo.getValueType(); lowerShiftLeftParts() local
8005 EVT VT = Lo.getValueType(); lowerShiftRightParts() local
8056 MVT VT = Op.getSimpleValueType(); lowerVectorMaskSplat() local
8153 MVT VT = Op.getOperand(0).getSimpleValueType(); lowerFixedLengthVectorExtendToRVV() local
8234 MVT VT = Op.getSimpleValueType(); lowerVectorTruncLike() local
8297 MVT VT = Op.getSimpleValueType(); lowerStrictFPExtendOrRoundLike() local
8351 MVT VT = Op.getSimpleValueType(); lowerVectorFPExtendOrRoundLike() local
8815 MVT VT = Op.getOperand(SplatOp - 1).getSimpleValueType(); lowerVectorIntrinsicScalars() local
9070 isValidEGW(int EGS,EVT VT,const RISCVSubtarget & Subtarget) isValidEGW() argument
9246 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
9326 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
9363 MVT VT = Op.getSimpleValueType(); getVCIXISDNodeWCHAIN() local
9416 MVT VT = Op->getSimpleValueType(0); LowerINTRINSIC_W_CHAIN() local
9498 MVT VT = Op->getSimpleValueType(0); LowerINTRINSIC_W_CHAIN() local
9571 MVT VT = Val.getSimpleValueType(); LowerINTRINSIC_VOID() local
9619 MVT VT = Op->getOperand(2).getSimpleValueType(); LowerINTRINSIC_VOID() local
10422 MVT VT = N.getSimpleValueType(); widenVectorOpsToi8() local
10618 MVT VT = Op.getSimpleValueType(); lowerSTEP_VECTOR() local
10764 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorLoadToRVV() local
10814 MVT VT = StoreVal.getSimpleValueType(); lowerFixedLengthVectorStoreToRVV() local
10858 MVT VT = Op.getSimpleValueType(); lowerMaskedLoad() local
10946 MVT VT = Val.getSimpleValueType(); lowerMaskedStore() local
10991 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorSetccToRVV() local
11019 MVT VT = Op.getSimpleValueType(); lowerVectorStrictFSetcc() local
11101 MVT VT = Op.getSimpleValueType(); lowerABS() local
11139 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorFCOPYSIGNToRVV() local
11159 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorSelectToRVV() local
11187 MVT VT = Op.getSimpleValueType(); lowerToScalableOp() local
11240 MVT VT = Op.getSimpleValueType(); lowerVPOp() local
11293 MVT VT = Op.getSimpleValueType(); lowerVPExtMaskOp() local
11326 MVT VT = Op.getSimpleValueType(); lowerVPSetCCMaskOp() local
11530 MVT VT = Op.getSimpleValueType(); lowerVPFPIntConvOp() local
11549 MVT VT = Op.getSimpleValueType(); lowerVPSpliceExperimental() local
11626 MVT VT = Op.getSimpleValueType(); lowerVPSplatExperimental() local
11647 MVT VT = Op.getSimpleValueType(); lowerVPReverseExperimental() local
11766 MVT VT = Op.getSimpleValueType(); lowerLogicVPOp() local
11794 MVT VT = Op.getSimpleValueType(); lowerVPStridedLoad() local
11843 MVT VT = StoreVal.getSimpleValueType(); lowerVPStridedStore() local
11882 MVT VT = Op.getSimpleValueType(); lowerMaskedGather() local
12006 MVT VT = Val.getSimpleValueType(); lowerMaskedScatter() local
12440 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
12601 EVT VT = N->getValueType(0); ReplaceNodeResults() local
12642 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
12839 EVT VT = N->getValueType(0); ReplaceNodeResults() local
12959 const EVT VT = N->getValueType(0); combineBinOpOfExtractToReduceTree() local
13153 EVT VT = N->getValueType(0); transformAddShlImm() local
13204 EVT VT = N->getValueType(0); combineSelectAndUse() local
13299 EVT VT = N->getValueType(0); transformAddImmMulImm() local
13358 EVT VT = N->getValueType(0); combineBinOpOfZExt() local
13401 EVT VT = N->getValueType(0); combineAddOfBooleanXor() local
13449 EVT VT = N->getValueType(0); combineSubOfBoolean() local
13493 EVT VT = N->getValueType(0); combineSubShiftToOrcB() local
13520 EVT VT = N->getValueType(0); performSUBCombine() local
13575 EVT VT = N->getValueType(0); combineDeMorganOfBoolean() local
13599 EVT VT = N->getValueType(0); combineTruncSelectToSMaxUSat() local
13665 EVT VT = N->getValueType(0); performTRUNCATECombine() local
13751 EVT VT = N->getValueType(0); combineOrOfCZERO() local
13825 EVT VT = N0.getValueType(); performXORCombine() local
13866 EVT VT = N->getValueType(0); expandMul() local
14016 EVT VT = N->getValueType(0); combineVectorMulToSraBitcast() local
14054 EVT VT = N->getValueType(0); performMULCombine() local
14109 EVT VT = N.getValueType(); narrowIndex() local
14175 EVT VT = N->getValueType(0); performSETCCCombine() local
14221 EVT VT = N->getValueType(0); performSIGN_EXTEND_INREGCombine() local
14367 MVT VT = Root->getSimpleValueType(0); getNarrowType() local
14489 MVT VT = OrigOperand.getSimpleValueType(); fillUpExtensionSupportForSplat() local
14553 MVT VT = OrigOperand.getSimpleValueType(); fillUpExtensionSupport() local
14581 MVT VT = OrigOperand.getSimpleValueType(); fillUpExtensionSupport() local
14694 MVT VT = Root->getSimpleValueType(0); getMaskAndVL() local
15309 EVT VT = N->getValueType(0); performFP_TO_INTCombine() local
15455 EVT VT = N->getValueType(0); performBITREVERSECombine() local
15737 EVT VT = Cond.getValueType(); tryDemorganOfBooleanCondition() local
15896 EVT VT = N->getValueType(0); tryFoldSelectIntoOp() local
15980 EVT VT = N->getValueType(0); useInversedSetcc() local
16032 EVT VT = N->getValueType(0); performBUILD_VECTORCombine() local
16094 EVT VT = InVec.getValueType(); performINSERT_VECTOR_ELTCombine() local
16162 EVT VT = N->getValueType(0); performCONCAT_VECTORSCombine() local
16349 EVT VT = N->getValueType(0); combineToVWMACC() local
16388 matchIndexAsShuffle(EVT VT,SDValue Index,SDValue Mask,SmallVector<int> & ShuffleMask) matchIndexAsShuffle() argument
16423 matchIndexAsWiderOp(EVT VT,SDValue Index,SDValue Mask,Align BaseAlign,const RISCVSubtarget & ST) matchIndexAsWiderOp() argument
16528 MVT VT = N->getSimpleValueType(0); combineTruncToVnclip() local
16755 MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
16787 EVT VT = N->getValueType(0); PerformDAGCombine() local
16921 EVT VT = N->getValueType(0); PerformDAGCombine() local
17036 EVT VT = N->getValueType(0); PerformDAGCombine() local
17061 const EVT VT = N->getValueType(0); PerformDAGCombine() local
17183 EVT VT = MSN->getValue()->getValueType(0); PerformDAGCombine() local
17256 EVT VT = N->getValueType(0); PerformDAGCombine() local
17278 EVT VT = N->getValueType(0); PerformDAGCombine() local
17421 EVT VT = N->getValueType(0); PerformDAGCombine() local
17443 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17454 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17486 EVT VT = N->getValueType(0); PerformDAGCombine() local
17497 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17550 MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17598 EVT VT = N->getValueType(0); PerformDAGCombine() local
17609 EVT VT = N->getValueType(0); PerformDAGCombine() local
17709 EVT VT = Op.getValueType(); targetShrinkDemandedConstant() local
19883 getPrefTypeAlign(EVT VT,SelectionDAG & DAG) getPrefTypeAlign() argument
20200 MVT VT = Outs[i].VT; CanLowerReturn() local
21225 EVT VT; getPreIndexedAddressParts() local
21268 EVT VT; getPostIndexedAddressParts() local
21344 decomposeMulByConstant(LLVMContext & Context,EVT VT,SDValue C) const decomposeMulByConstant() argument
21386 EVT VT = AddNode.getValueType(); isMulAddWithConstProfitable() local
21407 allowsMisalignedMemoryAccesses(EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMisalignedMemoryAccesses() argument
21576 isIntDivCheap(EVT VT,AttributeList Attr) const isIntDivCheap() argument
21619 EVT VT = getValueType(DL, VTy); isLegalInterleavedAccessType() local
21901 getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const getRegisterByName() argument
21975 getCustomCtpopCost(EVT VT,ISD::CondCode Cond) const getCustomCtpopCost() argument
22018 EVT VT = N->getValueType(0); BuildSDIVPow2() local
22029 shouldFoldSelectWithSingleBitTest(EVT VT,const APInt & AndMask) const shouldFoldSelectWithSingleBitTest() argument
22108 EVT VT = TLI->getValueType(DL, ElemTy); constructArgInfos() local
22122 EVT VT = ValueVTs[Value]; constructArgInfos() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
41 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentMemType()
48 return VT; in getEquivalentMemType()
183 for (MVT VT : MVT::integer_valuetypes()) in AMDGPUTargetLowering() local
184 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i64, VT, in AMDGPUTargetLowering()
187 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
188 if (VT == MVT::i64) in AMDGPUTargetLowering()
192 setLoadExtAction(Op, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
193 setLoadExtAction(Op, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
194 setLoadExtAction(Op, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp62 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
64 setLoadExtAction(N, VT, MVT::i1, Promote); in AVRTargetLowering()
65 setLoadExtAction(N, VT, MVT::i8, Expand); in AVRTargetLowering()
71 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
72 setOperationAction(ISD::ADDC, VT, Legal); in AVRTargetLowering()
73 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
74 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
75 setOperationAction(ISD::SUBE, VT, Legal); in AVRTargetLowering()
140 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
141 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); in AVRTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGenTypes/
H A DLowLevelType.cpp19 LLT::LLT(MVT VT) { in LLT() argument
20 if (VT.isVector()) { in LLT()
21 bool asVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector(); in LLT()
23 VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(), in LLT()
25 } else if (VT.isValid() && !VT.isScalableTargetExtVT()) { in LLT()
29 ElementCount::getFixed(0), VT.getSizeInBits(), /*AddressSpace=*/0); in LLT()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp170 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) { in addTypeForNEON() argument
171 if (VT != PromotedLdStVT) { in addTypeForNEON()
172 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
173 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
175 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
176 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
179 MVT ElemTy = VT.getVectorElementType(); in addTypeForNEON()
181 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
182 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
183 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp81 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) { in BPFTargetLowering()
82 if (VT == MVT::i32) { in BPFTargetLowering()
86 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom); in BPFTargetLowering()
89 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom); in BPFTargetLowering()
90 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom); in BPFTargetLowering()
91 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom); in BPFTargetLowering()
92 setOperationAction(ISD::ATOMIC_SWAP, VT, Custom); in BPFTargetLowering()
93 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom); in BPFTargetLowering()
96 for (auto VT : { MVT::i32, MVT::i64 }) { in BPFTargetLowering()
97 if (VT == MVT::i32 && !STI.getHasAlu32()) in BPFTargetLowering()
[all …]

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