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Searched refs:VT (Results 1 – 25 of 390) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/utils/TableGen/Basic/
H A DVTEmitter.cpp31 static void vTtoGetLlvmTyString(raw_ostream &OS, const Record *VT) { in vTtoGetLlvmTyString() argument
32 bool IsVector = VT->getValueAsBit("isVector"); in vTtoGetLlvmTyString()
33 bool IsRISCVVecTuple = VT->getValueAsBit("isRISCVVecTuple"); in vTtoGetLlvmTyString()
36 unsigned NElem = VT->getValueAsInt("nElem"); in vTtoGetLlvmTyString()
37 unsigned Sz = VT->getValueAsInt("Size"); in vTtoGetLlvmTyString()
45 OS << (VT->getValueAsBit("isScalable") ? "Scalable" : "Fixed") in vTtoGetLlvmTyString()
48 auto OutputVT = IsVector ? VT->getValueAsDef("ElementType") : VT; in vTtoGetLlvmTyString()
87 OS << ", " << VT->getValueAsInt("nElem") << ")"; in vTtoGetLlvmTyString()
94 for (auto *VT : Records.getAllDerivedDefinitions("ValueType")) { in run() local
95 auto Number = VT->getValueAsInt("Value"); in run()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp172 EVT VT = N->getValueType(0); in SelectExtractHigh() local
175 if (!VT.is64BitVector() || !LVT.is128BitVector() || in SelectExtractHigh()
176 Index != VT.getVectorNumElements()) in SelectExtractHigh()
186 EVT VT = Op.getValueType(); in SelectRoundingVLShr() local
188 if (ShtAmt > VT.getScalarSizeInBits() / 2 || Op.getOpcode() != ISD::ADD) in SelectRoundingVLShr()
193 Imm = APInt(VT.getScalarSizeInBits(), in SelectRoundingVLShr()
198 Imm = APInt(VT.getScalarSizeInBits(), in SelectRoundingVLShr()
249 template<MVT::SimpleValueType VT>
251 return SelectSVEAddSubImm(N, VT, Imm, Shift); in SelectSVEAddSubImm()
254 template <MVT::SimpleValueType VT, bool Negate>
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H A DAArch64ISelLowering.cpp178 static inline EVT getPackedSVEVectorVT(EVT VT) { in getPackedSVEVectorVT() argument
179 switch (VT.getSimpleVT().SimpleTy) { in getPackedSVEVectorVT()
218 static inline EVT getPromotedVTForPredicate(EVT VT) { in getPromotedVTForPredicate() argument
219 assert(VT.isScalableVector() && (VT.getVectorElementType() == MVT::i1) && in getPromotedVTForPredicate()
221 switch (VT.getVectorMinNumElements()) { in getPromotedVTForPredicate()
240 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType() argument
241 assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && in isPackedVectorType()
243 return VT.isFixedLengthVector() || in isPackedVectorType()
244 VT.getSizeInBits().getKnownMinValue() == AArch64::SVEBitsPerBlock; in isPackedVectorType()
462 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
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H A DAArch64FastISel.cpp180 bool isTypeLegal(Type *Ty, MVT &VT);
181 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
185 bool simplifyAddress(Address &Addr, MVT VT);
222 Register emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
224 bool emitStore(MVT VT, Register SrcReg, Address Addr,
226 bool emitStoreRelease(MVT VT, Register SrcReg, Register AddrReg,
233 Register emitAdd_ri_(MVT VT, Register Op0, int64_t Imm);
262 Register materializeInt(const ConstantInt *CI, MVT VT);
263 Register materializeFP(const ConstantFP *CFP, MVT VT);
314 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor() argument
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h45 bool operator==(EVT VT) const {
46 return !(*this != VT);
48 bool operator!=(EVT VT) const {
49 if (V.SimpleTy != VT.V.SimpleTy)
52 return LLVMTy != VT.LLVMTy;
74 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements,
76 MVT M = MVT::getVectorVT(VT.V, NumElements, IsScalable);
79 return getExtendedVectorVT(Context, VT, NumElements, IsScalable);
84 static EVT getVectorVT(LLVMContext &Context, EVT VT, ElementCount EC) { in getVectorVT()
85 MVT M = MVT::getVectorVT(VT.V, EC); in getVectorVT()
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H A DTargetLowering.h481 virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const { in shouldExpandGetActiveLaneMask() argument
492 virtual bool shouldExpandCttzElements(EVT VT) const { return true; } in shouldExpandCttzElements() argument
503 virtual bool shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const { in shouldExpandVectorMatch() argument
509 virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const { in shouldReassociateReduction() argument
531 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction() argument
533 if (VT.getVectorElementCount().isScalar()) in getPreferredVectorAction()
536 if (!VT.isPow2VectorType()) in getPreferredVectorAction()
573 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap() argument
576 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem() argument
597 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
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H A DSelectionDAG.h116 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
117 FastID(ID), VTs(VT), NumVTs(Num) {
672 LLVM_ABI SDVTList getVTList(EVT VT);
687 LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
689 LLVM_ABI SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
692 LLVM_ABI SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT,
696 LLVM_ABI SDValue getAllOnesConstant(const SDLoc &DL, EVT VT,
700 LLVM_ABI SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
704 LLVM_ABI SDValue getShiftAmountConstant(uint64_t Val, EVT VT,
706 LLVM_ABI SDValue getShiftAmountConstant(const APInt &Val, EVT VT,
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp220 EVT VT = getOptimalMemOpType(Context, Op, FuncAttributes); in findOptimalMemOpLowering() local
222 if (VT == MVT::Other) { in findOptimalMemOpLowering()
226 VT = MVT::LAST_INTEGER_VALUETYPE; in findOptimalMemOpLowering()
228 while (Op.getDstAlign() < (VT.getSizeInBits() / 8) && in findOptimalMemOpLowering()
229 !allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign())) in findOptimalMemOpLowering()
230 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering()
231 assert(VT.isInteger()); in findOptimalMemOpLowering()
241 if (VT.bitsGT(LVT)) in findOptimalMemOpLowering()
242 VT = LVT; in findOptimalMemOpLowering()
248 unsigned VTSize = VT.getSizeInBits() / 8; in findOptimalMemOpLowering()
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H A DDAGCombiner.cpp261 for (MVT VT : MVT::all_valuetypes()) in DAGCombiner() local
262 if (EVT(VT).isSimple() && VT != MVT::Other && in DAGCombiner()
263 TLI.isTypeLegal(EVT(VT)) && in DAGCombiner()
264 VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits) in DAGCombiner()
265 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue(); in DAGCombiner()
348 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
349 APInt DemandedElts = VT.isFixedLengthVector() in SimplifyDemandedBits()
350 ? APInt::getAllOnes(VT.getVectorNumElements()) in SimplifyDemandedBits()
400 SDValue foldBitwiseOpWithNeg(SDNode *N, const SDLoc &DL, EVT VT);
402 SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
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H A DSelectionDAG.cpp135 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType() argument
137 assert(VT.isFloatingPoint() && "Can only convert between FP types"); in isValueValidForType()
142 (void)Val2.convert(VT.getFltSemantics(), APFloat::rmNearestTiesToEven, in isValueValidForType()
1157 EVT VT = N->getValueType(0); in verifyNode() local
1159 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in verifyNode()
1164 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && in verifyNode()
1166 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && in verifyNode()
1233 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1234 if (VT.isExtended()) { in RemoveNodeFromCSEMaps()
1235 Erased = ExtendedValueTypeNodes.erase(VT); in RemoveNodeFromCSEMaps()
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H A DMatchContext.h40 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() argument
41 return TLI.isOperationLegal(Op, VT); in isOperationLegal()
44 bool isOperationLegalOrCustom(unsigned Op, EVT VT,
46 return TLI.isOperationLegalOrCustom(Op, VT, LegalOnly);
112 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { in getNode() argument
116 return DAG.getNode(VPOpcode, DL, VT, in getNode()
120 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
125 return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp}); in getNode()
128 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
133 return DAG.getNode(VPOpcode, DL, VT, in getNode()
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H A DLegalizeVectorOps.cpp768 MVT VT = Node->getSimpleValueType(0); in Promote() local
769 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); in Promote()
803 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || in Promote()
804 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
809 Res = DAG.getNode(ISD::VP_FP_ROUND, dl, VT, Res, in Promote()
812 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, in Promote()
816 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote()
826 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType(); in PromoteINT_TO_FP() local
827 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); in PromoteINT_TO_FP()
828 assert(NVT.getVectorNumElements() == VT.getVectorNumElements() && in PromoteINT_TO_FP()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp187 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
188 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
201 for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) { in X86TargetLowering()
202 setCondCodeAction(ISD::SETOEQ, VT, Expand); in X86TargetLowering()
203 setCondCodeAction(ISD::SETUNE, VT, Expand); in X86TargetLowering()
315 for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) { in X86TargetLowering()
316 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom); in X86TargetLowering()
317 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in X86TargetLowering()
329 for (MVT VT : {MVT::i32, MVT::v4i32, MVT::v8i32, MVT::v16i32, MVT::v2i64, in X86TargetLowering()
331 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Legal); in X86TargetLowering()
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H A DX86InterleavedAccess.cpp226 static MVT scaleVectorType(MVT VT) { in scaleVectorType() argument
227 unsigned ScalarSize = VT.getVectorElementType().getScalarSizeInBits() * 2; in scaleVectorType()
229 VT.getVectorNumElements() / 2); in scaleVectorType()
254 static void genShuffleBland(MVT VT, ArrayRef<int> Mask, in genShuffleBland() argument
257 assert(VT.getSizeInBits() >= 256 && in genShuffleBland()
259 unsigned NumOfElm = VT.getVectorNumElements(); in genShuffleBland()
284 static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix, in reorderSubVector() argument
299 genShuffleBland(VT, VPShuf, OptimizeShuf, (i / Stride) * 16, in reorderSubVector()
324 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
335 createUnpackShuffleMask(VT, MaskLowTemp1, true, false); in interleave8bitStride4VF8()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp55 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
57 VT.isInteger() ? RISCVISD::VMV_V_X_VL : RISCVISD::VFMV_V_F_VL; in PreprocessISelDAG()
61 if (VT.isInteger()) in PreprocessISelDAG()
64 Result = CurDAG->getNode(Opc, DL, VT, CurDAG->getUNDEF(VT), Src, VL); in PreprocessISelDAG()
72 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
77 assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() && in PreprocessISelDAG()
99 SDVTList VTs = CurDAG->getVTList({VT, MVT::Other}); in PreprocessISelDAG()
117 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
118 if (!VT.isVector()) in PreprocessISelDAG()
122 RISCVISD::VMSET_VL, DL, VT.changeVectorElementType(MVT::i1), VLMAX); in PreprocessISelDAG()
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H A DRISCVISelLowering.cpp181 auto addRegClassForRVV = [this](MVT VT) { in RISCVTargetLowering() argument
185 if (VT.getVectorMinNumElements() < MinElts) in RISCVTargetLowering()
188 unsigned Size = VT.getSizeInBits().getKnownMinValue(); in RISCVTargetLowering()
201 addRegisterClass(VT, RC); in RISCVTargetLowering()
204 for (MVT VT : BoolVecVTs) in RISCVTargetLowering() local
205 addRegClassForRVV(VT); in RISCVTargetLowering()
206 for (MVT VT : IntVecVTs) { in RISCVTargetLowering() local
207 if (VT.getVectorElementType() == MVT::i64 && in RISCVTargetLowering()
210 addRegClassForRVV(VT); in RISCVTargetLowering()
215 for (MVT VT : F16VecVTs) in RISCVTargetLowering() local
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H A DRISCVISelLowering.h64 int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
65 bool isFPImmLegal(const APFloat &Imm, EVT VT,
70 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
79 EVT VT) const override;
83 getNumRegisters(LLVMContext &Context, EVT VT,
90 EVT VT) const override;
93 CallingConv::ID CC, EVT VT,
98 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT,
104 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
123 shouldExpandBuildVectorWithShuffles(EVT VT,
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H A DRISCVSelectionDAGInfo.cpp32 EVT VT = N->getValueType(0); in verifyTargetNode() local
33 assert(VT.isScalableVector() && VT.getVectorElementType() == MVT::i32 && in verifyTargetNode()
35 assert(N->getOperand(0).getValueType() == VT && in verifyTargetNode()
36 N->getOperand(1).getValueType() == VT && in verifyTargetNode()
37 N->getOperand(2).getValueType() == VT && in verifyTargetNode()
42 MaskVT.getVectorElementCount() == VT.getVectorElementCount() && in verifyTargetNode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp103 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, in getFPLibCall() argument
110 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
111 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
112 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
113 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
114 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
482 MVT VT) { in getOUTLINE_ATOMIC() argument
483 if (!VT.isScalarInteger()) in getOUTLINE_ATOMIC()
485 uint64_t MemSize = VT.getScalarSizeInBits() / 8; in getOUTLINE_ATOMIC()
523 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC() argument
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H A DCallingConvLower.cpp90 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
103 MVT VT = Outs[i].VT; in CheckReturn() local
105 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
117 MVT VT = Outs[i].VT; in AnalyzeReturn() local
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in AnalyzeReturn()
130 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands()
165 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
167 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
170 << VT << '\n'; in AnalyzeCallResult()
178 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult() argument
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h272 SimpleValueType VT = EltTyTable[SimpleTy - FIRST_VALUETYPE]; in getVectorElementType() local
273 assert(VT != INVALID_SIMPLE_VALUE_TYPE && "Not a vector MVT!"); in getVectorElementType()
274 return VT; in getVectorElementType()
384 bool knownBitsGT(MVT VT) const { in knownBitsGT() argument
385 return TypeSize::isKnownGT(getSizeInBits(), VT.getSizeInBits()); in knownBitsGT()
390 bool knownBitsGE(MVT VT) const { in knownBitsGE() argument
391 return TypeSize::isKnownGE(getSizeInBits(), VT.getSizeInBits()); in knownBitsGE()
395 bool knownBitsLT(MVT VT) const { in knownBitsLT() argument
396 return TypeSize::isKnownLT(getSizeInBits(), VT.getSizeInBits()); in knownBitsLT()
401 bool knownBitsLE(MVT VT) const { in knownBitsLE() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
41 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentMemType()
48 return VT; in getEquivalentMemType()
183 for (MVT VT : MVT::integer_valuetypes()) in AMDGPUTargetLowering() local
184 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i64, VT, in AMDGPUTargetLowering()
187 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
188 if (VT == MVT::i64) in AMDGPUTargetLowering()
192 setLoadExtAction(Op, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
193 setLoadExtAction(Op, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
194 setLoadExtAction(Op, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGenTypes/
H A DLowLevelType.cpp19 LLT::LLT(MVT VT) { in LLT() argument
20 if (VT.isVector()) { in LLT()
21 bool asVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector(); in LLT()
23 VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(), in LLT()
25 } else if (VT.isValid() && !VT.isScalableTargetExtVT()) { in LLT()
29 ElementCount::getFixed(0), VT.getSizeInBits(), /*AddressSpace=*/0); in LLT()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp61 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
63 setLoadExtAction(N, VT, MVT::i1, Promote); in AVRTargetLowering()
64 setLoadExtAction(N, VT, MVT::i8, Expand); in AVRTargetLowering()
70 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
71 setOperationAction(ISD::ADDC, VT, Legal); in AVRTargetLowering()
72 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
73 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
74 setOperationAction(ISD::SUBE, VT, Legal); in AVRTargetLowering()
139 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
140 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); in AVRTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp175 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) { in addTypeForNEON() argument
176 if (VT != PromotedLdStVT) { in addTypeForNEON()
177 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
178 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
180 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
181 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
184 MVT ElemTy = VT.getVectorElementType(); in addTypeForNEON()
186 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
187 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
188 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
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