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Searched refs:VSCALE (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1448 VSCALE, enumerator
H A DSDPatternMatch.h1044 return UnaryOpc_match<Opnd>(ISD::VSCALE, Op);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp196 case ISD::VSCALE: return "vscale"; in getOperationName()
H A DSelectionDAG.cpp2103 return getNode(ISD::VSCALE, DL, VT, getConstant(MulImm, DL, VT)); in getVScale()
3518 case ISD::VSCALE: { in computeKnownBits()
4669 if (Val.getOpcode() == ISD::VSCALE && in isKnownToBeAPowerOfTwo()
6051 case ISD::VSCALE: { in isKnownNeverZero()
6529 if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes) in getNode()
6600 case ISD::VSCALE: in getNode()
7497 if (Opcode == ISD::ADD && N1.getOpcode() == ISD::VSCALE && in getNode()
7498 N2.getOpcode() == ISD::VSCALE) { in getNode()
7510 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
7599 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
H A DDAGCombiner.cpp1113 if ((N1.getOpcode() == ISD::VSCALE || in reassociationCanBreakAddressingModePattern()
1115 N1.getOperand(0).getOpcode() == ISD::VSCALE && in reassociationCanBreakAddressingModePattern()
1118 int64_t ScalableOffset = N1.getOpcode() == ISD::VSCALE in reassociationCanBreakAddressingModePattern()
3138 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
3146 N0.getOperand(1).getOpcode() == ISD::VSCALE && in visitADD()
3147 N1.getOpcode() == ISD::VSCALE) { in visitADD()
4360 if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) { in visitSUB()
4826 if (!UseVP && N0.getOpcode() == ISD::VSCALE && NC1) { in visitMUL()
10604 if (N0.getOpcode() == ISD::VSCALE && N1C) { in visitSHL()
H A DLegalizeIntegerTypes.cpp124 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break; in PromoteIntegerResult()
3127 case ISD::VSCALE: in ExpandIntegerResult()
H A DSelectionDAGBuilder.cpp4460 ISD::VSCALE, dl, VScaleTy, in visitGetElementPtr()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td377 def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp715 setOperationAction(ISD::VSCALE, XLenVT, Custom); in RISCVTargetLowering()
7400 case ISD::VSCALE: { in LowerOperation()
22346 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerFormalArguments()
22634 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp7515 if (VScale.getOpcode() == ISD::VSCALE) { in SelectAddrModeIndexedSVE()
H A DAArch64ISelLowering.cpp1882 setOperationAction(ISD::VSCALE, MVT::i32, Custom); in AArch64TargetLowering()
7438 case ISD::VSCALE: in LowerOperation()
19864 if (VS.getOpcode() != ISD::VSCALE) in performLastTrueTestVectorCombine()