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Searched refs:VReg1 (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp247 Register VReg1 = MIB.getReg(1); in selectMergeValues() local
248 (void)VReg1; in selectMergeValues()
249 assert(MRI.getType(VReg1).getSizeInBits() == 32 && in selectMergeValues()
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
279 Register VReg1 = MIB.getReg(1); in selectUnmergeValues() local
280 (void)VReg1; in selectUnmergeValues()
281 assert(MRI.getType(VReg1).getSizeInBits() == 32 && in selectUnmergeValues()
282 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
H A DARMISelLowering.cpp11044 Register VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
11045 BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1) in EmitSjLjDispatchBlock()
11049 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock()
11053 .addReg(VReg1) in EmitSjLjDispatchBlock()
11108 Register VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
11110 .addReg(VReg1, RegState::Define) in EmitSjLjDispatchBlock()
11115 .addReg(VReg1) in EmitSjLjDispatchBlock()
11181 Register VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
11182 BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1) in EmitSjLjDispatchBlock()
11186 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp680 Register VReg1 = MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass); in generateLoadForNewConst() local
682 BuildMI(*MF, MI->getDebugLoc(), get(PPC::ADDIStocHA8), VReg1) in generateLoadForNewConst()
706 .addReg(VReg1, getKillRegState(true)) in generateLoadForNewConst()