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Searched refs:VREV64 (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h205 VREV64, // reverse elements within 64-bit doublewords enumerator
H A DARMScheduleSwift.td565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
H A DARMISelLowering.cpp1788 MAKE_CASE(ARMISD::VREV64) in getTargetNodeName()
6361 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
6887 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp); in LowerVSETCC()
8553 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
8613 SDValue OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, Op.getOperand(0)); in LowerReverse_VECTOR_SHUFFLE()
8923 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
H A DARMInstrInfo.td294 def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
H A DARMInstrNEON.td6956 // VREV64 : Vector Reverse elements within 64-bit doublewords
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td685 def VREV64 : WOpInst<"vrev64", "..", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQfmQm",