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Searched refs:VREV16 (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h206 VREV16, // reverse elements within 16-bit halfwords enumerator
H A DARMScheduleSwift.td565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
H A DARMISelLowering.cpp1796 MAKE_CASE(ARMISD::VREV16) in getTargetNodeName()
8507 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
8875 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); in LowerVECTOR_SHUFFLE()
10322 unsigned RevOpcode = NumActiveLanes == 16 ? ARMISD::VREV16 : ARMISD::VREV32; in LowerVecReduce()
18805 unsigned Rev = VT == MVT::v4i32 ? ARMISD::VREV32 : ARMISD::VREV16; in PerformMVEExtCombine()
H A DARMInstrInfo.td270 def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
320 // bitconvert would have to emit a VREV16.8 instruction, whereas the
H A DARMInstrNEON.td7029 // VREV16 : Vector Reverse elements within 16-bit halfwords
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td639 def VREV16 : WOpInst<"vrev16", "..", "cUcPcQcQUcQPc", OP_REV16>;