| /freebsd/sys/contrib/openzfs/module/zfs/ |
| H A D | vdev_raidz_math_avx2.c | 48 #define VR0(r...) VR0_(r) macro
77 "vpxor 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n" \
85 "vpxor 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n" \
99 "vpxor %" VR0(r) ", %" VR4(r)", %" VR4(r) "\n" \
106 "vpxor %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
121 "vmovdqa %" VR0(r) ", %" VR4(r) "\n" \
128 "vmovdqa %" VR0(r) ", %" VR2(r) "\n" \
141 "vmovdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
149 "vmovdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
163 "vmovdqa %%" VR0(r) ", 0x00(%[DST])\n" \
[all …]
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| H A D | vdev_raidz_math_avx512bw.c | 52 #define VR0(r...) VR0_(r) macro
80 "vpxorq 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n" \
88 "vpxorq 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n" \
102 "vpxorq %" VR0(r) ", %" VR4(r)", %" VR4(r) "\n" \
109 "vpxorq %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
124 "vmovdqa64 %" VR0(r) ", %" VR4(r) "\n" \
131 "vmovdqa64 %" VR0(r) ", %" VR2(r) "\n" \
144 "vmovdqa64 0x00(%[SRC]), %%" VR0(r) "\n" \
152 "vmovdqa64 0x00(%[SRC]), %%" VR0(r) "\n" \
166 "vmovdqa64 %%" VR0(r) ", 0x00(%[DST])\n" \
[all …]
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| H A D | vdev_raidz_math_ssse3.c | 49 #define VR0(r...) VR0_(r) macro
78 "pxor 0x00(%[SRC]), %%" VR0(r) "\n" \
86 "pxor 0x00(%[SRC]), %%" VR0(r) "\n" \
100 "pxor %" VR0(r) ", %" VR4(r) "\n" \
107 "pxor %" VR0(r) ", %" VR2(r) "\n" \
122 "movdqa %" VR0(r) ", %" VR4(r) "\n" \
129 "movdqa %" VR0(r) ", %" VR2(r) "\n" \
142 "movdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
150 "movdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
164 "movdqa %%" VR0(r)", 0x00(%[DST])\n" \
[all …]
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| H A D | vdev_raidz_math_powerpc_altivec_common.h | 51 #define VR0(r...) VR0_(r) macro
147 "vxor " VR0(r) "," VR0(r) ",21\n" \
177 "vxor " VR0(r) "," VR0(r) ",21\n" \
192 "vxor " VR0(r) "," VR0(r) ",21\n" \
209 "vxor " VR4(r) "," VR4(r) "," VR0(r) "\n" \
218 "vxor " VR2(r) "," VR2(r) "," VR0(r) "\n" \
233 "vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
246 "vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
254 "vxor " VR0(r) "," VR0(r) "," VR0(r) "\n" \
268 "vor " VR4(r) "," VR0(r) "," VR0(r) "\n" \
[all …]
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| H A D | vdev_raidz_math_aarch64_neon_common.h | 54 #define VR0(r...) VR0_(r) macro
150 "eor " VR0(r) ".16b," VR0(r) ".16b,v21.16b\n" \
180 "eor " VR0(r) ".16b," VR0(r) ".16b,v21.16b\n" \
195 "eor " VR0(r) ".16b," VR0(r) ".16b,v21.16b\n" \
212 "eor " VR4(r) ".16b," VR4(r) ".16b," VR0(r) ".16b\n" \
221 "eor " VR2(r) ".16b," VR2(r) ".16b," VR0(r) ".16b\n" \
236 "eor " VR0(r) ".16b," VR0(r) ".16b," VR0(r) ".16b\n" \
249 "eor " VR0(r) ".16b," VR0(r) ".16b," VR0(r) ".16b\n" \
257 "eor " VR0(r) ".16b," VR0(r) ".16b," VR0(r) ".16b\n" \
271 "mov " VR4(r) ".16b," VR0(r) ".16b\n" \
[all …]
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| H A D | vdev_raidz_math_sse2.c | 50 #define VR0(r...) VR0_(r, 1, 2, 3, 4, 5, 6) macro
70 "pxor 0x00(%[SRC]), %%" VR0(r) "\n" \
78 "pxor 0x00(%[SRC]), %%" VR0(r) "\n" \
83 __asm("pxor 0x00(%[SRC]), %%" VR0(r) "\n" \
94 "pxor %" VR0(r) ", %" VR4(r) "\n" \
101 "pxor %" VR0(r) ", %" VR2(r) "\n" \
106 "pxor %" VR0(r) ", %" VR1(r)); \
118 "movdqa %" VR0(r) ", %" VR4(r) "\n" \
125 "movdqa %" VR0(r) ", %" VR2(r) "\n" \
130 "movdqa %" VR0(r) ", %" VR1(r)); \
[all …]
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| H A D | vdev_raidz_math_avx512f.c | 51 #define VR0(r...) VR0_(r) macro
94 "vpxorq 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n" \
108 "vpxorq %" VR0(r) ", %" VR4(r)", %" VR4(r) "\n" \
115 "vpxorq %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
130 "vmovdqa64 %" VR0(r) ", %" VR4(r) "\n" \
137 "vmovdqa64 %" VR0(r) ", %" VR2(r) "\n" \
148 "vmovdqa64 0x00(%[SRC]), %%" VR0(r) "\n" \
162 "vmovdqa64 %%" VR0(r) ", 0x00(%[DST])\n" \
186 "vpandq %" VR0(r)", %zmm30, %zmm26\n" \
194 "vpsllq $1, %" VR0(r)", %" VR0(r) "\n" \
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 207 Register VR0 = MRI.createVirtualRegister(RC); in expandLoadACC() local
215 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
216 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); in expandLoadACC()
232 Register VR0 = MRI.createVirtualRegister(RC); in expandStoreACC() local
238 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
239 TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0); in expandStoreACC()
265 Register VR0 = MRI.createVirtualRegister(RC); in expandCopyACC() local
272 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandCopyACC()
274 .addReg(VR0, RegState::Kill); in expandCopyACC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchAsmPrinter.cpp | 79 if (MO.getReg().id() >= LoongArch::VR0 && in PrintAsmOperand()
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| H A D | LoongArchISelLowering.cpp | 4670 const MCPhysReg ArgVRs[] = {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/Disassembler/ |
| H A D | LoongArchDisassembler.cpp | 108 Inst.addOperand(MCOperand::createReg(LoongArch::VR0 + RegNo)); in DecodeLSX128RegisterClass()
|