Searched refs:VQDMULH (Results 1 – 7 of 7) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 230 VQDMULH, // MVE vqdmulh instruction enumerator
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H A D | ARMScheduleA57.td | 1021 "VQDMULH(sl)?(v4i16|v2i32)", "VQRDMULH(sl)?(v4i16|v2i32)")>; 1029 "VQDMULH(sl)?(v8i16|v4i32)", "VQRDMULH(sl)?(v8i16|v4i32)")>;
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H A D | ARMScheduleSwift.td | 614 (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH",
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H A D | ARMISelLowering.cpp | 1810 MAKE_CASE(ARMISD::VQDMULH) in getTargetNodeName() 13403 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine() local 13404 SDValue Trunc = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, ExtVecVT, VQDMULH); in PerformVQDMULHCombine() 13420 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine() local 13421 Parts.push_back(VQDMULH); in PerformVQDMULHCombine() 18992 case ARMISD::VQDMULH: in PerformDAGCombine()
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H A D | ARMInstrNEON.td | 4395 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half 4396 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
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H A D | ARMInstrMVE.td | 1998 def MVEvqdmulh : SDNode<"ARMISD::VQDMULH", SDTIntBinOp>;
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
H A D | arm_neon.td | 323 def VQDMULH : SInst<"vqdmulh", "...", "siQsQi">;
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