/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | MVEVPTBlockPass.cpp | 74 if (CmpMI->modifiesRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST() 76 if (CmpMI->readsRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST() 134 if (Iter->definesRegister(ARM::VPR, /*TRI=*/nullptr) || in IsVPRDefinedOrKilledByBlock() 135 Iter->killsRegister(ARM::VPR, /*TRI=*/nullptr)) in IsVPRDefinedOrKilledByBlock()
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H A D | MVETPAndVPTOptimisationsPass.cpp | 934 Register VPR = Instr.getOperand(PIdx + 1).getReg(); in ReplaceConstByVPNOTs() local 935 if (!VPR.isVirtual()) in ReplaceConstByVPNOTs() 939 MachineInstr *Copy = MRI->getVRegDef(VPR); in ReplaceConstByVPNOTs() 963 if (LastVPTReg != 0 && LastVPTReg != VPR && LastVPTImm == Imm) { in ReplaceConstByVPNOTs() 966 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs() 972 VPR = LastVPTReg; in ReplaceConstByVPNOTs() 984 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs() 991 VPR = NewVPR; in ReplaceConstByVPNOTs() 995 LastVPTReg = VPR; in ReplaceConstByVPNOTs()
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H A D | ARMLowOverheadLoops.cpp | 90 return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR; in isVectorPredicated() 94 return MI->findRegisterDefOperandIdx(ARM::VPR, /*TRI=*/nullptr) != -1; in isVectorPredicate() 98 return MI.findRegisterUseOperandIdx(ARM::VPR, /*TRI=*/nullptr) != -1; in hasVPRUse() 229 assert((CurrentPredicates.size() || MI->getParent()->isLiveIn(ARM::VPR)) in CreateVPTBlock() 1024 if (RegMask.PhysReg == ARM::VPR) { in ValidateLiveOuts() 1236 if (!MO.isReg() || !MO.isUse() || MO.getReg() != ARM::VPR) in ValidateMVEInst() 1678 MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR); in ConvertVPTBlocks()
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H A D | ARMRegisterInfo.td | 203 // on the instruction they are used in and for VPR 32 was chosen such that it 205 def VPR : ARMReg<32, "vpr">; 410 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> { 468 // Scalar single and double precision floating point and VPR register class, 471 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
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H A D | ARMInstrVFP.td | 328 …let Defs = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D1… 338 …let Defs = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D1… 346 let Defs = [VPR, FPSCR, FPSCR_NZCV]; 347 …let Uses = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D1… 357 let Defs = [VPR, FPSCR, FPSCR_NZCV]; 358 …let Uses = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D1… 2545 // System level VPR/P0 -> GPR 2546 let Uses = [VPR] in 2616 // System level GPR -> VPR/P0 2617 let Defs = [VPR] in [all …]
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H A D | ARMExpandPseudoInsts.cpp | 1385 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81() 1396 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81() 1769 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
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H A D | ARMBaseInstrInfo.cpp | 882 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp() 991 } else if (DestReg == ARM::VPR) { in copyPhysReg() 997 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
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H A D | ARMInstrMVE.td | 4483 // example when moving between rGPR and VPR.P0 as part of predicate vector 6602 let Defs = [VPR]; 6714 let Defs = [VPR]; 6761 let Uses = [VPR];
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H A D | ARMInstrFormats.td | 238 // always either zero_reg or VPR, but needs to be modelled as an
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
H A D | RegisterInfoPOSIX_riscv64.h | 38 struct VPR { struct
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | VPlanTransforms.cpp | 110 for (VPRegionBlock *VPR : VPBlockUtils::blocksOnly<VPRegionBlock>(Iter)) { in sinkScalarOperands() 111 VPBasicBlock *EntryVPBB = VPR->getEntryBasicBlock(); in sinkScalarOperands() 112 if (!VPR->isReplicator() || EntryVPBB->getSuccessors().size() != 2) in sinkScalarOperands() 115 if (!VPBB || VPBB->getSingleSuccessor() != VPR->getExitingBasicBlock()) in sinkScalarOperands()
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/freebsd/contrib/llvm-project/llvm/include/llvm/ProfileData/ |
H A D | InstrProfData.inc | 515 getValueProfRecordNext(ValueProfRecord *VPR); 517 getValueProfRecordValueData(ValueProfRecord *VPR);
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/freebsd/contrib/llvm-project/compiler-rt/include/profile/ |
H A D | InstrProfData.inc | 515 getValueProfRecordNext(ValueProfRecord *VPR); 517 getValueProfRecordValueData(ValueProfRecord *VPR);
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 6250 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR() 6271 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR() 6464 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM() 6949 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP() 6986 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP() 6997 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT() 6998 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
H A D | tegra124-venice2.dts | 65 * it after having set the VPR up
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H A D | tegra124-jetson-tk1.dts | 74 * it after having set the VPR up
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H A D | tegra124-apalis.dtsi | 62 * it after having set the VPR up
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H A D | tegra124-apalis-v1.2.dtsi | 63 * it after having set the VPR up
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 3803 if (Regs.back().second == ARM::VPR) in CreateRegList() 3809 if (Regs.back().second == ARM::VPR) in CreateRegList() 4719 if (Reg == ARM::VPR && in parseRegisterList()
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/freebsd/contrib/ncurses/misc/ |
H A D | terminfo.src | 3546 # + in ECMA-48 cursor movement, VPR and HPR fail. Others work. 3626 # supports CHA, VPA, VPR, but no other ECMA-48 cursor movement such as HPA 3670 # supports CBT, CHA, VPA, CNL, CPL, VPR (no HPA, CHT, HPR) 7484 # CBT, CHT, HPR, CNL,CPL, VPR do not work 24543 # VPR Vert. Position Relative \E [ Pn e 1 FE - (R) 24670 # (R) Some ANSI.SYS versions accept VPR, but more commonly `ANSI' terminals 24671 # use CUD for this function and ignore VPR. ECMA calls it `Line Position
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