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Searched refs:VPR (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanUnroll.cpp54 void unrollReplicateRegionByUF(VPRegionBlock *VPR);
127 void UnrollState::unrollReplicateRegionByUF(VPRegionBlock *VPR) { in unrollReplicateRegionByUF() argument
128 VPBlockBase *InsertPt = VPR->getSingleSuccessor(); in unrollReplicateRegionByUF()
130 auto *Copy = VPR->clone(); in unrollReplicateRegionByUF()
134 auto Part0 = vp_depth_first_shallow(VPR->getEntry()); in unrollReplicateRegionByUF()
327 auto *VPR = dyn_cast<VPRegionBlock>(VPB); in unrollBlock() local
328 if (VPR) { in unrollBlock()
329 if (VPR->isReplicator()) in unrollBlock()
330 return unrollReplicateRegionByUF(VPR); in unrollBlock()
335 RPOT(VPR->getEntry()); in unrollBlock()
H A DVPlanTransforms.cpp130 for (VPRegionBlock *VPR : VPBlockUtils::blocksOnly<VPRegionBlock>(Iter)) { in sinkScalarOperands()
131 VPBasicBlock *EntryVPBB = VPR->getEntryBasicBlock(); in sinkScalarOperands()
132 if (!VPR->isReplicator() || EntryVPBB->getSuccessors().size() != 2) in sinkScalarOperands()
135 if (!VPBB || VPBB->getSingleSuccessor() != VPR->getExitingBasicBlock()) in sinkScalarOperands()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp70 if (CmpMI->modifiesRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
72 if (CmpMI->readsRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
130 if (Iter->definesRegister(ARM::VPR, /*TRI=*/nullptr) || in IsVPRDefinedOrKilledByBlock()
131 Iter->killsRegister(ARM::VPR, /*TRI=*/nullptr)) in IsVPRDefinedOrKilledByBlock()
H A DMVETPAndVPTOptimisationsPass.cpp932 Register VPR = Instr.getOperand(PIdx + 1).getReg(); in ReplaceConstByVPNOTs() local
933 if (!VPR.isVirtual()) in ReplaceConstByVPNOTs()
937 MachineInstr *Copy = MRI->getVRegDef(VPR); in ReplaceConstByVPNOTs()
961 if (LastVPTReg != 0 && LastVPTReg != VPR && LastVPTImm == Imm) { in ReplaceConstByVPNOTs()
964 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
970 VPR = LastVPTReg; in ReplaceConstByVPNOTs()
982 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
990 VPR = NewVPR; in ReplaceConstByVPNOTs()
994 LastVPTReg = VPR; in ReplaceConstByVPNOTs()
H A DARMLowOverheadLoops.cpp88 return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR; in isVectorPredicated()
92 return MI->findRegisterDefOperandIdx(ARM::VPR, /*TRI=*/nullptr) != -1; in isVectorPredicate()
96 return MI.findRegisterUseOperandIdx(ARM::VPR, /*TRI=*/nullptr) != -1; in hasVPRUse()
226 assert((CurrentPredicates.size() || MI->getParent()->isLiveIn(ARM::VPR)) in CreateVPTBlock()
1018 if (RegMask.PhysReg == ARM::VPR) { in ValidateLiveOuts()
1230 if (!MO.isReg() || !MO.isUse() || MO.getReg() != ARM::VPR) in ValidateMVEInst()
1672 MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR); in ConvertVPTBlocks()
H A DARMRegisterInfo.td203 // on the instruction they are used in and for VPR 64 was chosen such that it
205 def VPR : ARMReg<64, "vpr">;
410 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> {
477 // Scalar single and double precision floating point and VPR register class,
480 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
H A DARMInstrVFP.td341 …let Defs = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D1…
351 …let Defs = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D1…
359 let Defs = [VPR, FPSCR, FPSCR_NZCV];
360 …let Uses = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D1…
370 let Defs = [VPR, FPSCR, FPSCR_NZCV];
371 …let Uses = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D1…
2574 // System level VPR/P0 -> GPR
2575 let Uses = [VPR] in
2645 // System level GPR -> VPR/P0
2646 let Defs = [VPR] in
[all …]
H A DARMExpandPseudoInsts.cpp1384 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1395 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1806 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
H A DARMBaseInstrInfo.cpp707 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp()
818 } else if (DestReg == ARM::VPR) { in copyPhysReg()
824 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
H A DARMInstrMVE.td4417 // example when moving between rGPR and VPR.P0 as part of predicate vector
6534 let Defs = [VPR];
6646 let Defs = [VPR];
6693 let Uses = [VPR];
H A DARMInstrFormats.td228 // always either zero_reg or VPR, but needs to be modelled as an
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfoPOSIX_riscv64.h40 struct VPR { struct
/freebsd/contrib/llvm-project/llvm/include/llvm/ProfileData/
H A DInstrProfData.inc527 getValueProfRecordNext(ValueProfRecord *VPR);
529 getValueProfRecordValueData(ValueProfRecord *VPR);
/freebsd/contrib/llvm-project/compiler-rt/include/profile/
H A DInstrProfData.inc527 getValueProfRecordNext(ValueProfRecord *VPR);
529 getValueProfRecordValueData(ValueProfRecord *VPR);
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp6256 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6277 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6481 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6973 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
7010 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
7021 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
7022 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-venice2.dts65 * it after having set the VPR up
H A Dtegra124-jetson-tk1.dts74 * it after having set the VPR up
H A Dtegra124-apalis.dtsi62 * it after having set the VPR up
H A Dtegra124-apalis-v1.2.dtsi63 * it after having set the VPR up
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp1790 if (SPRRegs || DPRRegs || Reg == ARM::VPR) { in getRegisterListOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp3804 if (Regs.back().second == ARM::VPR) in CreateRegList()
3810 if (Regs.back().second == ARM::VPR) in CreateRegList()
3814 } else if (Regs.front().second == ARM::VPR) { in CreateRegList()
4664 else if (Reg == ARM::VPR) in parseRegisterList()
4739 if (Reg == ARM::VPR && in parseRegisterList()
/freebsd/contrib/ncurses/misc/
H A Dterminfo.src3549 # + in ECMA-48 cursor movement, VPR and HPR fail. Others work.
3630 # supports CHA, VPA, VPR, but no other ECMA-48 cursor movement such as HPA
3724 # supports CBT, CHA, VPA, CNL, CPL, VPR (no HPA, CHT, HPR)
7616 # CBT, CHT, HPR, CNL,CPL, VPR do not work
8335 # - fails vttest for REP, SL, SR, CBT, CHT, VPR
24940 # VPR Vert. Position Relative \E [ Pn e 1 FE - (R)
25067 # (R) Some ANSI.SYS versions accept VPR, but more commonly `ANSI' terminals
25068 # use CUD for this function and ignore VPR. ECMA calls it `Line Position