| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 723 unsigned VOffset = 0; in getMachineOpValue() local
742 ++VOffset; in getMachineOpValue()
764 unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset in getMachineOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 3199 Register VOffset = MI.getOperand(4 + OpOffset).getReg(); in selectBufferLoadLds() local
3201 getIConstantVRegValWithLookThrough(VOffset, *MRI); in selectBufferLoadLds()
3239 .addReg(VOffset) in selectBufferLoadLds()
3246 MIB.addReg(VOffset); in selectBufferLoadLds()
3322 Register VOffset; in selectGlobalLoadLds() local
3336 VOffset = Off; in selectGlobalLoadLds()
3344 if (!VOffset) { in selectGlobalLoadLds()
3345 VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectGlobalLoadLds()
3346 BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_MOV_B32_e32), VOffset) in selectGlobalLoadLds()
3355 MIB.addReg(VOffset); in selectGlobalLoadLds()
[all …]
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| H A D | AMDGPULegalizerInfo.cpp | 5838 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferStore() local
5849 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferStore()
5876 .addUse(VOffset) // voffset in legalizeBufferStore()
5892 Register VIndex, Register VOffset, Register SOffset, in buildBufferLoad() argument
5900 .addUse(VOffset) // voffset in buildBufferLoad()
5949 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferLoad() local
5972 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferLoad()
6013 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
6033 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
6040 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
[all …]
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| H A D | AMDGPUISelDAGToDAG.h | 169 SDValue &VOffset, SDValue &Offset) const;
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| H A D | AMDGPUISelDAGToDAG.cpp | 1765 SDValue &VOffset, in SelectGlobalSAddr() argument
1795 VOffset = SDValue(VMov, 0); in SelectGlobalSAddr()
1824 VOffset = ZextRHS; in SelectGlobalSAddr()
1832 VOffset = ZextLHS; in SelectGlobalSAddr()
1852 VOffset = SDValue(VMov, 0); in SelectGlobalSAddr()
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| H A D | SIRegisterInfo.cpp | 1388 int64_t VOffset) { in buildSpillLoadStore() argument
1398 .addImm(VOffset) in buildSpillLoadStore()
1404 .addImm(VOffset) in buildSpillLoadStore()
1410 .addImm(VOffset); in buildSpillLoadStore()
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| H A D | AMDGPURegisterBankInfo.cpp | 1363 Register VOffset; in applyMappingSBufferLoad() local
1366 unsigned MMOOffset = setBufferOffsets(B, MI.getOperand(2).getReg(), VOffset, in applyMappingSBufferLoad()
1409 .addUse(VOffset) // voffset in applyMappingSBufferLoad()
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| H A D | SIISelLowering.cpp | 9714 SDValue VOffset = Op.getOperand(5 + OpOffset); in LowerINTRINSIC_VOID() local
9715 bool HasVOffset = !isNullConstant(VOffset); in LowerINTRINSIC_VOID()
9748 VOffset })); in LowerINTRINSIC_VOID()
9752 Ops.push_back(VOffset); in LowerINTRINSIC_VOID()
9816 SDValue VOffset; in LowerINTRINSIC_VOID() local
9830 VOffset = RHS.getOperand(0); in LowerINTRINSIC_VOID()
9837 if (!VOffset) in LowerINTRINSIC_VOID()
9838 VOffset = SDValue( in LowerINTRINSIC_VOID()
9841 Ops.push_back(VOffset); in LowerINTRINSIC_VOID()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41461 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local
41465 WordMask[i + VOffset] = VMask[i] + VOffset; in combineTargetShuffle()
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