Searched refs:VMOVN (Results 1 – 7 of 7) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 212 VMOVN, // MVE vmovn enumerator
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H A D | ARMScheduleSwift.td | 630 def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VMOVN", "VMOVL")>;
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H A D | ARMScheduleA57.td | 1216 def : InstRW<[A57Write_3cyc_1V], (instregex "VMOVN")>;
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H A D | ARMISelLowering.cpp | 1802 MAKE_CASE(ARMISD::VMOVN) in getTargetNodeName() 8900 return DAG.getNode(ARMISD::VMOVN, dl, VT, V2, V1, in LowerVECTOR_SHUFFLE() 8903 return DAG.getNode(ARMISD::VMOVN, dl, VT, V1, V2, in LowerVECTOR_SHUFFLE() 8906 return DAG.getNode(ARMISD::VMOVN, dl, VT, V1, V1, in LowerVECTOR_SHUFFLE() 15701 ARMISD::VMOVN, DL, VT, in PerformShuffleVMOVNCombine() 15707 ARMISD::VMOVN, DL, VT, in PerformShuffleVMOVNCombine() 18641 ARMISD::VMOVN, DL, VT, in PerformMVETruncCombine() 18647 ARMISD::VMOVN, DL, VT, in PerformMVETruncCombine() 18987 case ARMISD::VMOVN: in PerformDAGCombine()
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H A D | ARMInstrMVE.td | 4878 def MVEvmovn : SDNode<"ARMISD::VMOVN", SDTARMVEXT>; 4900 // Match the IR intrinsic for a predicated VMOVN. This regards the Qm input
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H A D | ARMInstrNEON.td | 6768 // VMOVN : Vector Narrowing Move 6769 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
H A D | arm_neon.td | 568 def VMOVN : IInst<"vmovn", "<Q", "silUsUiUl">;
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