| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFixCortexA57AES1742098Pass.cpp | 163 case ARM::VMOVDRR: in isSafeAESInput()
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| H A D | ARMInstrVFP.td | 26 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
1202 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
1286 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1318 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1321 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1324 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
1327 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
2795 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
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| H A D | ARMFeatures.td | 257 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
259 // True if VMOVSR will be favored over VMOVDRR.
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| H A D | ARMISelLowering.h | 115 VMOVDRR, // Two gprs to double. enumerator
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| H A D | ARMInstructionSelector.cpp | 258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
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| H A D | ARMScheduleM55.td | 458 def : InstRW<[M55WriteFloatE3], (instregex "VINSH$", "VMOVH$", "VMOVHR$", "VMOVSR$", "VMOVDRR$")>; // VINS, VMOVX, to-FP reg movs
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| H A D | ARMExpandPseudoInsts.cpp | 1321 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) in CMSEClearFPRegsV8()
1492 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSESaveClearFPRegsV8()
1732 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSERestoreFPRegsV8()
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| H A D | ARMScheduleSwift.td | 641 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
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| H A D | ARMISelLowering.cpp | 1743 MAKE_CASE(ARMISD::VMOVDRR) in getTargetNodeName()
2242 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
2259 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
4377 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
5271 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
6045 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
6116 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
6283 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
7168 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi); in LowerConstantFP()
15058 if (InDouble.getOpcode() == ARMISD::VMOVDRR && Subtarget->hasFP64()) in PerformVMOVRRDCombine()
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| H A D | ARMScheduleA57.td | 807 def : InstRW<[A57Write_8cyc_1L_1I], (instregex "VMOVDRR")>;
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| H A D | ARMFastISel.cpp | 2044 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
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| H A D | ARMInstrNEON.td | 6658 // ARMvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
6659 def : Pat<(v2i32 (ARMvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
6661 def : Pat<(v2f32 (ARMvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
7499 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
7501 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
7504 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
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| H A D | ARMBaseInstrInfo.cpp | 5459 case ARM::VMOVDRR: in getRegSequenceLikeInputs()
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