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Searched refs:VMOV (Results 1 – 17 of 17) sorted by relevance

/freebsd/bin/ed/
H A Dundo.c108 case VMOV: in pop_undo_stack()
H A Ded.h78 #define VMOV 3 macro
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM55.td112 // Some VMOV's can go down either pipeline. FIXME: This M55Write2IntFPE2 is
113 // intended to model the VMOV taking either Int or FP for 2 cycles. It is not
421 // Some VMOV's can go down either pipeline.
459 def : InstRW<[M55WriteFloatE2], (instregex "VMOVD$", "VMOVS$", "VMOVR")>; // Other VMOV's
H A DARMScheduleM7.td447 // VMOV
449 (instregex "VMOV(H|S)$", "FCONST(H|S)")>;
455 (instregex "VMOV(DRR|RRD|RRS|SRR)")>;
H A DARMFeatures.td246 // True if VMOV will be favored over VGETLNi32.
249 "Has slow VGETLNi32 - prefer VMOV">;
252 // True if VMOV will be favored over VDUP.
255 "Has slow VDUP32 - prefer VMOV">;
H A DARMScheduleM85.td632 // VMOV
634 (instregex "VMOV(H|S)$", "FCONST(H|S)")>;
648 (instregex "VMOV(RRD|RRS)")>;
H A DARMScheduleA57.td794 // VMOV: 3cyc "F0/F1" for imm/reg
796 def : InstRW<[A57Write_3cyc_1V], (instregex "VMOV(D|S|H)(cc)?$")>;
804 def : InstRW<[A57Write_5cyc_1L, A57Write_5cyc_1L], (instregex "VMOV(RRS|RRD)")>;
1212 "VMOV(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v1i64|v2i64|v2f32|v4f32)",
H A DARMScheduleSwift.td627 (instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc",
H A DARMInstrNEON.td6211 // VMOV : Vector Move (Register)
6217 // VMOV : Vector Move (Immediate)
6309 // In this case we do not canonicalize VMVN to VMOV
6328 // TODO: add "VMOV <-> VMVN" conversion for cases like
6351 // VMOV : Vector Get Lane (move scalar to ARM core register)
6508 // VMOV : Vector Set Lane (move ARM core register to scalar)
9000 // VMOV/VMVN takes an optional datatype suffix
H A DARMInstrVFP.td2807 // VMOV can accept optional 32-bit or less data type suffix suffix.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedSapphireRapids.td581 "^VMOV(A|U)P(D|S)Zrr((_REV)?)$",
1267 "^VMOV(D|SH|SL)DUPZ128rm$",
1600 def : InstRW<[SPRWriteResGroup125], (instregex "^VMOV(W|SHZ)mr$")>;
1615 "^VMOV(D|SH|SL)DUP(Y|Z)rm$",
1616 "^VMOV(D|SH|SL)DUPZ256rm$",
1664 "^VMOV(A|U)P(D|S)Zrmk(z?)$",
1665 "^VMOV(D|SH|SL)DUPZrmk(z?)$",
1868 "^VMOV(A|U)P(D|S)Z(128|256)rrk(z?)((_REV)?)$",
2017 "^VMOV(A|U)P(D|S)Z128rmk(z?)$",
2018 "^VMOV(D|SH|SL)DUPZ128rmk(z?)$",
[all …]
H A DX86InstrVecCompiler.td124 (SrcTy (!cast<Instruction>("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>;
H A DX86SchedIceLake.td1218 def: InstRW<[ICXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
1297 def: InstRW<[ICXWriteResGroup92], (instregex "VMOV(SD|SS)Zrm(b?)",
H A DX86SchedLunarlakeP.td2313 "^VMOV(D|SH|SL)DUPYrm$",
H A DX86SchedSkylakeServer.td1188 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
H A DX86SchedAlderlakeP.td1337 "^VMOV(D|SH|SL)DUPYrm$",
H A DX86InstrAVX512.td39 // Prefer over VMOV*rrk Pat<>
54 let isCommutable = IsKZCommutable, // Prefer over VMOV*rrkz Pat<>