Searched refs:VMEM (Results 1 – 5 of 5) sorted by relevance
83 int checkVMEMHazards(MachineInstr* VMEM);
71 VMEM = 1u << 4, enumerator78 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |2411 else if (((SGMask & SchedGroupMask::VMEM) != SchedGroupMask::NONE) && in canAddMI()2630 if ((InvertedMask & SchedGroupMask::VMEM) == SchedGroupMask::NONE) in invertSchedBarrierMask()2635 InvertedMask &= ~SchedGroupMask::VMEM; in invertSchedBarrierMask()
181 // If XNACK is enabled, the VMEM latency can be worse.238 …"VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution…268 "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"289 "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"1106 "VMEM instructions of the same type write VGPR results in order"
700 int GCNHazardRecognizer::checkVMEMHazards(MachineInstr* VMEM) { in checkVMEMHazards() argument704 int WaitStatesNeeded = checkSoftClauseHazards(VMEM); in checkVMEMHazards()712 for (const MachineOperand &Use : VMEM->uses()) { in checkVMEMHazards()
320 // MASK = 0x0000 0010: ALL VMEM instructions may be scheduled across SCHED_BARRIER.321 // MASK = 0x0000 0020: VMEM read instructions may be scheduled across SCHED_BARRIER.322 // MASK = 0x0000 0040: VMEM write instructions may be scheduled across SCHED_BARRIER.