Searched refs:VLo (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4265 SDValue VLo = DAG.getZExtOrTrunc(EVLLo, DL, ResVT); in SplitVecOp_VP_CttzElements()
4271 DAG.getSetCC(DL, getSetCCResultType(ResVT), ResLo, VLo, ISD::SETNE); in SplitVecOp_VP_CttzElements()
4274 DAG.getNode(ISD::ADD, DL, ResVT, VLo, ResHi));
4261 SDValue VLo = DAG.getZExtOrTrunc(EVLLo, DL, ResVT); SplitVecOp_VP_CttzElements() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10472 auto [VLo, VHi] = DAG.SplitScalar(V, dl, MVT::i32, MVT::i32); in createGPRPairNode()
10475 std::swap (VLo, VHi); in createGPRPairNode()
10480 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 25950 auto [VLo, VHi] = DAG.SplitScalar(V, dl, MVT::i64, MVT::i64); in createGPRPairNode()
25952 std::swap (VLo, VHi); in createGPRPairNode()
25957 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
|