Searched refs:VLo (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4566 SDValue VLo = DAG.getZExtOrTrunc(EVLLo, DL, ResVT); in SplitVecOp_VP_CttzElements() local
4572 DAG.getSetCC(DL, getSetCCResultType(ResVT), ResLo, VLo, ISD::SETNE); in SplitVecOp_VP_CttzElements()
4575 DAG.getNode(ISD::ADD, DL, ResVT, VLo, ResHi)); in SplitVecOp_VP_CttzElements()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10533 auto [VLo, VHi] = DAG.SplitScalar(V, dl, MVT::i32, MVT::i32); in createGPRPairNodei64()
10536 std::swap(VLo, VHi); in createGPRPairNodei64()
10537 return createGPRPairNode2xi32(DAG, VLo, VHi); in createGPRPairNodei64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 27460 auto [VLo, VHi] = DAG.SplitScalar(V, DL, MVT::i64, MVT::i64); in createGPRPairNode()
27462 std::swap (VLo, VHi); in createGPRPairNode()
27467 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
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